mpc8569e Freescale Semiconductor, Inc, mpc8569e Datasheet - Page 35

• Manufacturer Part Number: mpc8569e
• Description: Mpc8569e Powerquicc Iii Integrated Processor Hardware Specifications
• Manufacturer: Freescale Semiconductor, Inc

Freescale Semiconductor
Notes:
1. All multiplexed signals are listed only once and do not reoccur.
2. This pin is a reset configuration pin. It has a weak internal pull-up P-FET which is enabled only when the processor is in the
3. When configured as I2C, this pin is an open drain signal and recommend a pull-up resistor (1 kΩ) be placed on this pin to
4. This pin has a weak internal pull-up resistor (~20 kΩ).
5. This pin is an open drain signal.
6. Recommend a weak pull-up resistor (2–10 kΩ) be placed on this pin to OV
7. This pin requires a 200-Ω pull-down to ground.
8. Do not connect.
9. Recommend a weak pull-down resistor (2–10 kΩ) be placed on this pin to GND.
10. These are test signals for factory use only and must be pulled up (100 Ω–1 kΩ) to OV
11. These pins must not be pulled down during power-on reset.
12. See AN4232 MPC8569E PowerQUICC III Design Checklist for the required PLL filters to be attached to the AV
13. These pins are connected to the V
14. This pin selects the voltage of eLBC interface (BV
15. This pin selects the voltage of UCC1 and UCC3 interfaces (LV
16. This pin selects the voltage of UCC2 and UCC4 interfaces (LV
17. This pin requires a 100-Ω pull down to ground.
18. The value of LA[24:27] during reset sets the CCB clock to SYSCLK PLL ratio. These pins require 4.7-kΩ pull-up or pull-down
19. The value of QE_PE[27:29] during reset sets the DDR clock PLL settings. These pins require 4.7-kΩ pull up or pull down
20. The value of LALE, LGPL2/LOE/LFRE and LBCTL at reset set the e500 core clock to CCB Clock PLL ratio. These pins
21. The value of LCS[3:7] at reset sets the QE PLL settings. These pins require 4.7-kΩ pull up or pull down resistors. See
22. The value of QE_PB[27:28], QE_PC4 and QE_PD4 at reset sets the Boot ROM location. These pins require 4.7-kΩ pull up
23. These pins are sampled at reset for general-purpose configuration use by software. The value of LAD[0:15] at reset sets the
24. These pins must not be pulled up during power-on reset.
25. This output is actively driven during reset rather than being three-stated during reset.
reset state. This pull-up is designed such that it can be overpowered by an external 4.7-kΩ pull-down resistor. However, if the
signal is intended to be high after reset, and if there is any device on the net which might pull down the value of the net at
reset, then a pull-up or active driver is needed.
OV
and regulation.
resistors. See AN4232 MPC8569E PowerQUICC III Design Checklist for more details.
resistors. See AN4232 MPC8569E PowerQUICC III Design Checklist for more details.
require 4.7-kΩ pull-up or pull-down resistors. See the AN4232 MPC8569E PowerQUICC III Design Checklist for more details.
AN4232 MPC8569E PowerQUICC III Design Checklist for more details.
or pull down resistors. See the MPC8569E PowerQUICC III Integrated Host Processor Family Reference Manual for details
upper 16 bits of the GPPORCR
DD
. When configured as SD, this pin is not open drain and does not require a pull-up.
AGND_SRDS
Signal
XGND
XGND
MPC8569E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 0
1
Table 1. MPC8569E Pinout Listing (continued)
DD
/GND planes internally and may be used by the core power supply to improve tracking
Package Pin Number
DD
). This pin has internal weak pull down.
W23
Y21
U25
DD
DD
1). This pin has internal weak pull down.
2). This pin has internal weak pull down.
DD
.
SerDes Transceiver
SerDes Transceiver
SerDes PLL GND
Pad GND
Pad GND
Pin Type
DD
for normal machine operation.
Power Supply
—
—
—
DD
Pinout List
pin.
Note
—
—
—
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