mpc8260aec Freescale Semiconductor, Inc, mpc8260aec Datasheet
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... Technical Data MPC8260AEC/D Rev. 0.9 8/2003 MPC826xA (HiP4) Family Hardware Specifications This document contains detailed information on power considerations, DC/AC electrical characteristics, and AC timing specifications for .25 µ m (HiP4) devices in the PowerQUICC II™ MPC8260 communications processor family. These devices include the MPC8260, the MPC8255, the MPC8264, the MPC8265, and the MPC8266. Throughout this document, these devices are collectively referred to as the MPC826xA ...
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Figure 1 shows the block diagram for the MPC826, the HiP4 superset device. Shaded portions indicate functionality that is not available on all devices; refer to the notes. 16 Kbytes I-Cache I-MMU G2 Core 16 Kbytes D-Cache D-MMU Communication Processor ...
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High-performance (6.6–7.65 SPEC95 benchmark at 300 MHz; 1.68 MIPs/MHz without inlining and 1.90 Dhrystones MIPS/MHz with — Supports bus snooping for data cache coherency — Floating-point unit (FPU) • Separate power supply for internal logic and for I/O • ...
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Dedicated interface logic for SDRAM • CPU core can be disabled and the device can be used in slave mode to an external core • Communications processor module (CPM) — Embedded 32-bit communications processor (CP) uses a RISC architecture ...
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Supports two groups of four TDM channels for a total of eight TDMs – 2,048 bytes of SI RAM – Bit or byte resolution – Independent transmit and receive routing, frame synchronization – Supports T1, CEPT, T1/E1, T3/E3, pulse ...
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Internal rate mode (sub-rate)—FCC transfers only the data cells using the required data rate. The TC layer generates idle/unassigned cells to maintain the line bit rate. — Supports TC-layer and PMD-WIRE interface (according to the ATM-Forum af-phy-0063.000) — Cell ...
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DC Electrical Characteristics This section describes the DC electrical characteristics for the MPC826xA. Table 1 shows the maximum electrical ratings. Rating 2 Core supply voltage 2 PLL supply voltage 3 I/O supply voltage 4 Input voltage Junction temperature Storage ...
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Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (either GND or V Figure 2 shows the undershoot and overshoot voltage of the 60x and local bus ...
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Table 3. DC Electrical Characteristics Characteristic I = 7.0mA ABB/IRQ2 TS A[0-31] TT[0-4] TBST TSIZE[0–3] AACK ARTRY DBG DBB/IRQ3 D[0-63] DP(0)/RSRV/EXT_BR2 DP(1)/IRQ1/EXT_BG2 DP(2)/TLBISYNC/IRQ2/EXT_DBG2 DP(3)/IRQ3/EXT_BR3/CKSTP_OUT DP(4)/IRQ4/EXT_BG3/CORE_SREST DP(5)/TBEN/IRQ5/EXT_DBG3 DP(6)/CSE(0)/IRQ6 DP(7)/CSE(1)/IRQ7 PSDVAL TA TEA GBL/IRQ1 CI/BADDR29/IRQ2 WT/BADDR30/IRQ3 L2_HIT/IRQ4 CPU_BG/BADDR31/IRQ5 CPU_DBG ...
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Table 3. DC Electrical Characteristics Characteristic I = 5.3mA OL CS[0-9] CS(10)/BCTL1 CS(11)/AP(0) BADDR[27–28] ALE BCTL0 PWE(0:7)/PSDDQM(0:7)/PBS(0:7) PSDA10/PGPL0 PSDWE/PGPL1 POE/PSDRAS/PGPL2 PSDCAS/PGPL3 PGTA/PUPMWAIT/PGPL4/PPBS PSDAMUX/PGPL5 LWE[0–3]LSDDQM[0–3]/LBS[0–3]/PCI_CFG[0–3 LSDA10/LGPL0/PCI_MODCKH0 LSDWE/LGPL1/PCI_MODCKH1 LOE/LSDRAS/LGPL2/PCI_MODCKH2 LSDCAS/LGPL3/PCI_MODCKH3 LGTA/LUPMWAIT/LGPL4/LPBS LSDAMUX/LGPL5/PCI_MODCK LWR MODCK1/AP(1)/TC(0)/BNKSEL(0) MODCK2/AP(2)/TC(1)/BNKSEL(1) MODCK3/AP(3)/TC(2)/BNKSEL( 3.2mA OL 3 L_A14/PAR ...
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Thermal Characteristics Table 4 describes thermal characteristics. Table 4. Thermal Characteristics for 480 TBGA Package Characteristics Junction to ambient 4 Junction to board 5 Junction to case 1 Assumes a single layer board with no thermal vias 2 Natural ...
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Layout Practices Each V pin should be provided with a low-impedance path to the board’s power supply. Each ground pin CC should likewise be provided with a low-impedance path to ground. The power supply pins drive distinct groups of ...
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Output Buffers 60x bus Local bus Memory controller Parallel I/O PCI 1 These are typical values at 65˚ C. The impedance may vary by ±25% with process and temperature. Table 7 lists CPM output characteristics. Table 7. AC Characteristics for ...
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Figure 3 shows the FCC external clock. Serial ClKin sp16b FCC input signals FCC output signals Note: When GFMR[TCI FCC output signals Note: When GFMR[TCI Figure 4 shows the FCC internal clock. BRG_OUT sp16a FCC input ...
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Figure 5 shows the SCC/SMC/SPI/I Serial CLKin SCC/SMC/SPI/I2C input signals (See note.) SCC/SMC/SPI/I2C output signals (See note.) Note: There are four possible timing conditions for SCC and SPI: 1. Input sampled on the rising edge and output driven on the ...
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Figure 7 shows TDM input and output signals. Serial CLKin TDM input signals TDM output signals Note: There are four possible TDM timing conditions: 1. Input sampled on the rising edge and output driven on the rising edge (shown). 2. ...
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Table 10 lists SIU input characteristics. Table 9. AC Characteristics for SIU Inputs Spec Number Max Min sp11 sp10 AACK/ARTRY/TA/TS/TEA/DBG/BG/BR sp12 sp10 Data bus in normal mode sp13 sp10 Data bus in ECC and PARITY modes sp14 sp10 DP pins ...
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CLKin AACK/ARTRY/TA/TS/TEA/ DBG/BG/BR input signals DATA bus normal mode input signal All other input signals PSDVAL/TEA/TA output signals ADD/ADD_atr/BADDR/CI/ GBL/WT output signals DATA bus output signals All other output signals Figure 10 shows signal behavior for all parity modes (including ...
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Figure 11 shows signal behavior in MEMC mode. CLKin V_CLK Memory controller signals Generally, all MPC826xA bus and system output signals are driven from the rising edge of the input clock (CLKin). Memory controller signals, however, trigger on four points ...
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The UPM machine outputs change on the internal tick determined by the memory controller programming; the AC specifications are relative to the internal tick. Note that SDRAM and GPCM machine outputs change on CLKin’s rising edge. 1.3 Clock Configuration Modes ...
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Input Clock MODCK_H–MODCK[1–3] Frequency 0001_000 33 MHz 0001_001 33 MHz 0001_010 33 MHz 0001_011 33 MHz 0001_100 33 MHz 0001_101 33 MHz 0001_110 33 MHz 0001_111 33 MHz 0010_000 33 MHz 0010_001 33 MHz 0010_010 33 MHz 0010_011 33 MHz ...
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Table 13. Clock Configuration Modes Input Clock MODCK_H–MODCK[1–3] Frequency 0100_001 0100_010 0100_011 0100_100 0100_101 0100_110 0100_111 0101_000 0101_001 0101_010 0101_011 0101_100 0101_101 66 MHz 0101_110 66 MHz 0101_111 66 MHz 0110_000 66 MHz 0110_001 66 MHz 0110_010 66 MHz 0110_011 ...
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Table 13. Clock Configuration Modes Input Clock MODCK_H–MODCK[1–3] Frequency 0111_111 66 MHz 1000_000 66 MHz 1000_001 66 MHz 1000_010 66 MHz 1000_011 66 MHz 1000_100 66 MHz 1 Because of speed dependencies, not all of the possible configurations in Table ...
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PCI Host Mode The frequencies listed in Table 15 and Table 16 are for the purpose of illustration only. Users must select a mode and input bus frequency so that the resulting configuration does not exceed the frequency rating ...
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Table 16. Clock Configuration Modes in PCI Host Mode (Continued) Input Clock MODCK_H – 1 Frequency Multiplication MODCK[1–3] (Bus) Factor 3 0100_000 33 MHz 3 0100_001 33 MHz 3 0100_010 33 MHz 3 0100_011 33 MHz 0101_000 66 MHz 0101_001 ...
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Table 16. Clock Configuration Modes in PCI Host Mode (Continued) Input Clock CPM MODCK_H – 1 Frequency Multiplication MODCK[1–3] (Bus) Factor 1001_100 66 MHz 1010_000 100 MHz 1010_001 100 MHz 1010_010 100 MHz 1010_011 100 MHz 1010_100 100 MHz 1011_000 ...
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PCI Agent Mode The frequencies listed in Table 17 and Table 18 are for the purpose of illustration only. Users must select a mode and input bus frequency so that the resulting configuration does not exceed the frequency rating ...
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Table 18. Clock Configuration Modes in PCI Agent Mode (Continued) Input Clock CPM MODCK_H – Frequency Multiplication MODCK[1–3] 1,2 (PCI) Factor 0011_010 66/33 MHz 2/4 0011_011 66/33 MHz 2/4 0011_100 66/33 MHz 2/4 0100_000 66/33 MHz 3/6 0100_001 66/33 MHz ...
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Table 18. Clock Configuration Modes in PCI Agent Mode (Continued) Input Clock CPM MODCK_H – Frequency Multiplication MODCK[1–3] 1,2 (PCI) Factor 1001_000 66/33 MHz 1001_001 66/33 MHz 1001_010 66/33 MHz 1001_011 66/33 MHz 1001_100 66/33 MHz 1010_000 66/33 MHz 1010_001 ...
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Table 19 shows the pinout list of the MPC826xA. Table 20 defines conventions and acronyms used in Table 19. Pin Name BR BG ABB/IRQ2 A10 A11 A12 A13 A14 ...
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Pin Name A29 A30 A31 TT0 TT1 TT2 TT3 TT4 TBST TSIZ0 TSIZ1 TSIZ2 TSIZ3 AACK ARTRY DBG DBB/IRQ3 D10 D11 D12 D13 D14 D15 D16 D17 32 MPC826xA (HiP4) ...
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Pin Name D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 D32 D33 D34 D35 D36 D37 D38 D39 D40 D41 D42 D43 D44 D45 D46 D47 D48 D49 D50 D51 D52 MOTOROLA MPC826xA (HiP4) ...
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Pin Name D53 D54 D55 D56 D57 D58 D59 D60 D61 D62 D63 DP0/RSRV/EXT_BR2 IRQ1/DP1/EXT_BG2 IRQ2/DP2/TLBISYNC/EXT_DBG2 IRQ3/DP3/CKSTP_OUT/EXT_BR3 IRQ4/DP4/CORE_SRESET/EXT_BG3 IRQ5/DP5/TBEN/EXT_DBG3 IRQ6/DP6/CSE0 IRQ7/DP7/CSE1 PSDVAL TA TEA GBL/IRQ1 CI/BADDR29/IRQ2 WT/BADDR30/IRQ3 L2_HIT/IRQ4 CPU_BG/BADDR31/IRQ5 CPU_DBG CPU_BR CS0 CS1 CS2 CS3 CS4 CS5 34 MPC826xA (HiP4) ...
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Pin Name CS6 CS7 CS8 CS9 CS10/BCTL1 CS11/AP0 BADDR27 BADDR28 ALE BCTL0 PWE0/PSDDQM0/PBS0 PWE1/PSDDQM1/PBS1 PWE2/PSDDQM2/PBS2 PWE3/PSDDQM3/PBS3 PWE4/PSDDQM4/PBS4 PWE5/PSDDQM5/PBS5 PWE6/PSDDQM6/PBS6 PWE7/PSDDQM7/PBS7 PSDA10/PGPL0 PSDWE/PGPL1 POE/PSDRAS/PGPL2 PSDCAS/PGPL3 PGTA/PUPMWAIT/PGPL4/PPBS PSDAMUX/PGPL5 1 LWE0/LSDDQM0/LBS0/PCI_CFG0 1 LWE1/LSDDQM1/LBS1/PCI_CFG1 1 LWE2/LSDDQM2/LBS2/PCI_CFG2 1 LWE3/LSDDQM3/LBS3/PCI_CFG3 1 LSDA10/LGPL0/PCI_MODCKH0 1 LSDWE/LGPL1/PCI_MODCKH1 LOE/LSDRAS/LGPL2/PCI_MODCKH2 1 ...
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Pin Name 1 L_A14/PAR 1 L_A15/FRAME /SMI 1 L_A16/TRDY 1 L_A17/IRDY /CKSTP_OUT 1 L_A18/STOP 1 L_A19/DEVSEL 1 L_A20/IDSEL 1 L_A21/PERR 1 L_A22/SERR 1 L_A23/REQ0 1 1 L_A24/REQ1 /HSEJSW 1 L_A25/GNT0 1 1 L_A26/GNT1 /HSLED 1 1 L_A27/GNT2 /HSENUM 1 L_A28/RST ...
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Pin Name 1 LCL_D17/AD17 1 LCL_D18/AD18 1 LCL_D19/AD19 1 LCL_D20/AD20 1 LCL_D21/AD21 1 LCL_D22/AD22 1 LCL_D23/AD23 1 LCL_D24/AD24 1 LCL_D25/AD25 1 LCL_D26/AD26 1 LCL_D27/AD27 1 LCL_D28/AD28 1 LCL_D29/AD29 1 LCL_D30/AD30 1 LCL_D31/AD31 1 1 LCL_DP0/C0 /BE0 1 1 LCL_DP1/C1 /BE1 ...
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Pin Name XFC CLKIN1 PA0/RESTART1/DREQ3/FCC2_UTM_TXADDR2 PA1/REJECT1/FCC2_UTM_TXADDR1/DONE3 PA2/CLK20/FCC2_UTM_TXADDR0/DACK3 PA3/CLK19/FCC2_UTM_RXADDR0/DACK4/L1RXD1A2 PA4/REJECT2/FCC2_UTM_RXADDR1/DONE4 PA5/RESTART2/DREQ4/FCC2_UTM_RXADDR2 PA6/L1RSYNCA1 PA7/SMSYN2/L1TSYNCA1/L1GNTA1 PA8/SMRXD2/L1RXD0A1/L1RXDA1 PA9/SMTXD2/L1TXD0A1 PA10/FCC1_UT8_RXD0/FCC1_UT16_RXD8/MSNUM5 PA11/FCC1_UT8_RXD1/FCC1_UT16_RXD9/MSNUM4 PA12/FCC1_UT8_RXD2/FCC1_UT16_RXD10/MSNUM3 PA13/FCC1_UT8_RXD3/FCC1_UT16_RXD11/MSNUM2 PA14/FCC1_UT8_RXD4/FCC1_UT16_RXD12/FCC1_RXD3 PA15/FCC1_UT8_RXD5/FCC1_UT16_RXD13/FCC1_RXD2 PA16/FCC1_UT8_RXD6/FCC1_UT16_RXD14/FCC1_RXD1 PA17/FCC1_UT8_RXD7/FCC1_UT16_RXD15/FCC1_RXD0/FCC1_RXD PA18/FCC1_UT8_TXD7/FCC1_UT16_TXD15/FCC1_TXD0/FCC1_TXD PA19/FCC1_UT8_TXD6/FCC1_UT16_TXD14/FCC1_TXD1 PA20/FCC1_UT8_TXD5/FCC1_UT16_TXD13/FCC1_TXD2 PA21/FCC1_UT8_TXD4/FCC1_UT16_TXD12/FCC1_TXD3 PA22/FCC1_UT8_TXD3/FCC1_UT16_TXD11 PA23/FCC1_UT8_TXD2/FCC1_UT16_TXD10 PA24/FCC1_UT8_TXD1/FCC1_UT16_TXD9/MSNUM1 PA25/FCC1_UT8_TXD0/FCC1_UT16_TXD8/MSNUM0 PA26/FCC1_UTM_RXCLAV/FCC1_UTS_RXCLAV/FCC1_MII_RX_ER PA27/FCC1_UT_RXSOC/FCC1_MII_RX_DV PA28/FCC1_UTM_RXENB/FCC1_UTS_RXENB/FCC1_MII_TX_EN PA29/FCC1_UT_TXSOC/FCC1_MII_TX_ER PA30/FCC1_UTM_TXCLAV/FCC1_UTS_TXCLAV/FCC1_MII_CRS/ FCC1_RTS PA31/FCC1_UTM_TXENB/FCC1_UTS_TXENB/FCC1_MII_COL PB4/FCC3_TXD3/FCC2_UT8_RXD0/L1RSYNCA2/FCC3_RTS 38 MPC826xA ...
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Pin Name PB5/FCC3_TXD2/FCC2_UT8_RXD1/L1TSYNCA2/L1GNTA2 PB6/FCC3_TXD1/FCC2_UT8_RXD2/L1RXDA2/L1RXD0A2 PB7/FCC3_TXD0/FCC3_TXD/FCC2_UT8_RXD3/L1TXDA2/L1TXD0A2 PB8/FCC2_UT8_TXD3/FCC3_RXD0/FCC3_RXD/TXD3/L1RSYNCD1 PB9/FCC2_UT8_TXD2/FCC3_RXD1/L1TXD2A2/L1TSYNCD1/L1GNTD1 PB10/FCC2_UT8_TXD1/FCC3_RXD2/L1RXDD1 PB11/FCC3_RXD3/FCC2_UT8_TXD0/L1TXDD1 PB12/FCC3_MII_CRS/L1CLKOB1/L1RSYNCC1/TXD2 PB13/FCC3_MII_COL/L1RQB1/L1TSYNCC1/L1GNTC1/L1TXD1A2 PB14/FCC3_MII_TX_EN/RXD3/L1RXDC1 PB15/FCC3_MII_TX_ER/RXD2/L1TXDC1 PB16/FCC3_MII_RX_ER/L1CLKOA1/CLK18 PB17/FCC3_MII_RX_DV/L1RQA1/CLK17 PB18/FCC2_UT8_RXD4/FCC2_RXD3/L1CLKOD2/L1RXD2A2 PB19/FCC2_UT8_RXD5/FCC2_RXD2/L1RQD2/L1RXD3A2 PB20/FCC2_UT8_RXD6/FCC2_RXD1/L1RSYNCD2/L1TXD1A1 PB21/FCC2_UT8_RXD7/FCC2_RXD0/FCC2_RXD/L1TSYNCD2/L1GNTD2/ L1TXD2A1 PB22/FCC2_UT8_TXD7/FCC2_TXD0/FCC2_TXD/L1RXD1A1/L1RXDD2 PB23/FCC2_UT8_TXD6/FCC2_TXD1/L1RXD2A1/L1TXDD2 PB24/FCC2_UT8_TXD5/FCC2_TXD2/L1RXD3A1/L1RSYNCC2 PB25/FCC2_UT8_TXD4/FCC2_TXD3/L1TSYNCC2/L1GNTC2/L1TXD3A1 PB26/FCC2_MII_CRS/FCC2_UT8_TXD1/L1RXDC2 PB27/FCC2_MII_COL/FCC2_UT8_TXD0/L1TXDC2 PB28/FCC2_MII_RX_ER/FCC2_RTS/L1TSYNCB2/L1GNTB2/TXD1 PB29/FCC2_UTM_RXCLAV/FCC2_UTS_RXCLAV/L1RSYNCB2/ FCC2_MII_TX_EN PB30/FCC2_MII_RX_DV/FCC2_UT_TXSOC/L1RXDB2 PB31/FCC2_MII_TX_ER/FCC2_UT_RXSOC/L1TXDB2 PC0/DREQ1/BRGO7/SMSYN2/L1CLKOA2 PC1/DREQ2/BRGO6/L1RQA2 PC2/FCC3_CD/FCC2_UT8_TXD3/DONE2 PC3/FCC3_CTS/FCC2_UT8_TXD2/DACK2/CTS4 PC4/FCC2_UTM_RXENB/FCC2_UTS_RXENB/SI2_L1ST4/FCC2_CD PC5/FCC2_UTM_TXCLAV/FCC2_UTS_TXCLAV/SI2_L1ST3/FCC2_CTS PC6/FCC1_CD/L1CLKOC1/FCC1_UTM_RXADDR2/FCC1_UTS_RXADDR/ FCC1_UTM_RXCLAV1 MOTOROLA ...
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Pin Name PC7/FCC1_CTS/L1RQC1/FCC1_UTM_TXADDR2/FCC1_UTS_TXADDR2/ FCC1_UTM_TXCLAV1 PC8/CD4/RENA4/FCC1_UT16_TXD0/SI2_L1ST2/CTS3 PC9/CTS4/CLSN4/FCC1_UT16_TXD1/SI2_L1ST1/L1TSYNCA2/L1GNTA2 PC10/CD3/RENA3/FCC1_UT16_TXD2/SI1_L1ST4/FCC2_UT8_RXD3 PC11/CTS3/CLSN3/L1CLKOD1/L1TXD3A2/FCC2_UT8_RXD2 PC12/CD2/RENA2/SI1_L1ST3/FCC1_UTM_RXADDR1/ FCC1_UTS_RXADDR1 PC13/CTS2/CLSN2/L1RQD1/FCC1_UTM_TXADDR1/ FCC1_UTS_TXADDR1 PC14/CD1/RENA1/FCC1_UTM_RXADDR0/FCC1_UTS_RXADDR0 PC15/CTS1/CLSN1/SMTXD2/FCC1_UTM_TXADDR0/ FCC1_UTS_TXADDR0 PC16/CLK16/TIN4 PC17/CLK15/TIN3/BRGO8 PC18/CLK14/TGATE2 PC19/CLK13/BRGO7/SPICLK PC20/CLK12/TGATE1 PC21/CLK11/BRGO6 PC22/CLK10/DONE1 PC23/CLK9/BRGO5/DACK1 PC24/FCC2_UT8_TXD3/CLK8/TOUT4 PC25/FCC2_UT8_TXD2/CLK7/BRGO4 PC26/CLK6/TOUT3/TMCLK PC27/FCC3_TXD/FCC3_TXD0/CLK5/BRGO3 PC28/CLK4/TIN1/TOUT2/CTS2/CLSN2 PC29/CLK3/TIN2/BRGO2/CTS1/CLSN1 PC30/FCC2_UT8_TXD3/CLK2/TOUT1 PC31/CLK1/BRGO1 PD4/BRGO8/L1TSYNCD1/L1GNTD1/FCC3_RTS/SMRXD2 PD5/FCC1_UT16_TXD3/DONE1 PD6/FCC1_UT16_TXD4/DACK1 PD7/SMSYN1/FCC1_UTM_TXADDR3/FCC1_UTS_TXADDR3/ FCC2_UTM_TXADDR4/FCC1_TXCLAV2 PD8/SMRXD1/FCC2_UT_TXPRTY/BRGO5 PD9/SMTXD1/FCC2_UT_RXPRTY/BRGO3 PD10/L1CLKOB2/FCC2_UT8_RXD1/L1RSYNCB1/BRGO4 40 ...
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Pin Name PD11/L1RQB2/FCC2_UT8_RXD0/L1TSYNCB1/L1GNTB1 PD12/SI1_L1ST2/L1RXDB1 PD13/SI1_L1ST1/L1TXDB1 PD14/FCC1_UT16_RXD0/L1CLKOC2/I2CSCL PD15/FCC1_UT16_RXD1/L1RQC2/I2CSDA PD16/FCC1_UT_TXPRTY/L1TSYNCC1/L1GNTC1/SPIMISO PD17/FCC1_UT_RXPRTY/BRGO2/SPIMOSI PD18/FCC1_UTM_RXADDR4/FCC1_UTS_RXADDR4/ FCC1_UTM_RXCLAV3/FCC2_UTM_RXADDR3/SPICLK PD19/FCC1_UTM_TXADDR4/FCC1_UTS_TXADDR4/ FCC1_UTM_TXCLAV3/FCC2_UTM_TXADDR3/SPISEL/BRGO1 PD20/RTS4/TENA4/FCC1_UT16_RXD2/L1RSYNCA2 PD21/TXD4/FCC1_UT16_RXD3/L1RXD0A2/L1RXDA2 PD22/RXD4/FCC1_UT16_TXD5/L1TXD0A2/L1TXDA2 PD23/RTS3/TENA3/FCC1_UT16_RXD4/L1RSYNCD1 PD24/TXD3/FCC1_UT16_RXD5/L1RXDD1 PD25/RXD3/FCC1_UT16_TXD6/L1TXDD1 PD26/RTS2/TENA2/FCC1_UT16_RXD6/L1RSYNCC1 PD27/TXD2/FCC1_UT16_RXD7/L1RXDC1 PD28/RXD2/FCC1_UT16_TXD7/L1TXDC1 PD29/RTS1/TENA1/FCC1_UTM_RXADDR3/FCC1_UTS_RXADDR3/ FCC1_UTM_RXCLAV2/FCC2_UTM_RXADDR4 PD30/FCC2_UTM_TXENB/FCC2_UTS_TXENB/TXD1 PD31/RXD1 VCCSYN VCCSYN1 GNDSYN 1,3 CLKIN2 4 SPARE4 1,5 PCI_MODE 4 SPARE6 6 THERMAL0 6 ...
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Pin Name I/O power Core Power Ground 1 MPC8265 and MPC8266 only. 2 The default configuration of the CPM pins (PA[0–31], PB[4–31], PC[0–31], PD[4–31]) is input. To prevent excessive DC current recommended to either pull unused pins to ...
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Package Description The following sections provide the package parameters and mechanical dimensions for the MPC826xA. 1.5.1 Package Parameters Package parameters are provided in Table 21. The package type is a 37.5 x 37.5 mm, 480-lead TBGA. Package Outline Interconnects ...
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Mechanical Dimensions Figure 15 provides the mechanical dimensions and bottom surface nomenclature of the 480 TBGA package. Figure 15. Mechanical Dimensions and Bottom Surface Nomenclature 44 MPC826xA (HiP4) Family Hardware Specifications Notes: 1. Dimensions and Tolerancing per ASME Y14.5M-1994. ...
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Ordering Information Figure 16 provides an example of the Motorola part numbering nomenclature for the MPC826xA. In addition to the processor frequency, the part numbering scheme also consists of a part modifier that indicates any enhancement(s) in the part ...
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Table 22. Document Revision History (Continued) Revision Date 0.5 3/2002 • Table 19: Modified notes to pins AE11 and AF25. • Table 19: Addition of note to pins AA1 and AG4 (Therm0 and Therm1). 0.6 3/2002 • Table 19: Modified ...
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THIS PAGE INTENTIONALLY LEFT BLANK MOTOROLA MPC826xA (HiP4) Family Hardware Specifications Document Revision History 47 ...
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... Motorola and the Stylized M Logo are registered in the U.S. Patent and Trademark Office. digital dna is a trademark of Motorola, Inc. All other product or service names are the property of their respective owners. Motorola, Inc Equal Opportunity/Affirmative Action Employer. © Motorola, Inc. 2003 MPC8260AEC/D ...