mpc82x54a Megawin Technology, mpc82x54a Datasheet - Page 33

• Manufacturer Part Number: mpc82x54a
• Description: 8-bit Micro-controller
• Manufacturer: Megawin Technology

Watch Dog Timer
MEGAWIN
The watch dog timer in MPC82x54A consists of an 8-bit pre-scalar timer and a 15-bit timer.
The timer is one-time enabled by setting ENW. Clearing ENW can not stop WDT counting.
When the WDT is enabled, software should always reset the timer by writing 1 to CLRW bit
before the WDT overflows. If MPC82x54A is out of control by any disturbance, that means the
CPU can not run the software normally then WDT may miss the “writing 1 to CLRW” and
overflow will come. WDT overflow reset the CPU to restart. Associated with the WDTCR
SFR, a NVM option register bytes named OR3 are designed to enable WDT and initiate
WDTCR with initial states. See Option Register description to know in more details.
To make good use of the watch-dog-timer, the user should take notice on SFR WDTCR.
SFR: WDTCR (WDT Control Register)
Fosc/12
WRF: = When WDT overflows, this bit is set. It can be cleared by software.
ENW: = Control bit to enable Watch-Dog-Timer. (One-time enabled, can not be disabled)
CLRW: = Set this bit to recount WDT. Hardware will automatically clear this bit.
IDLE
WRF
Bit-7
0:= (default)
1:=
Disable Watch Dog Timer
Enable Watch Dog Timer start counting
Bit-6
-
ENW
Bit-5
1/256
1/128
1/64
1/32
1/16
8-bit prescalar
1/8
1/4
1/2
MPC82x54A Data Sheet
CLRW
WRF
Bit-4
-
ENW
WIDL
CLRW
Bit-3
WIDL
PS2
WDTCR Register
PS1
Bit-2
PS2
15-bit timer
PS0
Bit-1
PS1
Bit-0
PS0
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