mpc8641 Freescale Semiconductor, Inc, mpc8641 Datasheet - Page 31

• Manufacturer Part Number: mpc8641
• Description: Integrated Host Processor Hardware Specifications
• Manufacturer: Freescale Semiconductor, Inc

1
At recommended operating conditions with L/TV
clock to synchronously generate transmit data and outputs an echoed copy of the transmit clock back out
onto the TSECn_GTX_CLK pin (while transmit data appears on TSECn_TXD[7:0], for example). It is
intended that external receivers capture eTSEC transmit data using the clock on TSECn_GTX_CLK as a
source-synchronous timing reference. Typically, the clock edge that launched the data can be used, since
the clock is delayed by the eTSEC to allow acceptable set-up margin at the receiver. Note that there is
relationship between the maximum FIFO speed and the platform speed. For more information see
Section 18.4.2, “Platform to FIFO
A summary of the FIFO AC specifications appears in
At recommended operating conditions with L/TV
RX_CLK clock period (GMII mode)
RX_CLK clock period (Encoded mode)
RX_CLK duty cycle
RX_CLK peak-to-peak jitter
Rise time RX_CLK (20%–80%)
Fall time RX_CLK (80%–20%)
RXD[7:0], RX_DV, RX_ER setup time to RX_CLK
RXD[7:0], RX_DV, RX_ER hold time to RX_CLK
Freescale Semiconductor
TX_CLK, GTX_CLK clock period (GMII mode)
TX_CLK, GTX_CLK clock period (Encoded mode)
TX_CLK, GTX_CLK duty cycle
TX_CLK, GTX_CLK peak-to-peak jitter
Rise time TX_CLK (20%–80%)
Fall time TX_CLK (80%–20%)
FIFO data TXD[7:0], TX_ER, TX_EN setup time to GTX_CLK
GTX_CLK to FIFO data TXD[7:0], TX_ER, TX_EN hold time
±100 ppm tolerance on RX_CLK frequency
Parameter/Condition
MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 2
The phase between the output clocks TSEC1_GTX_CLK and
TSEC2_GTX_CLK (ports 1 and 2) is no more than 100 ps. The phase
between the output clocks TSEC3_GTX_CLK and TSEC4_GTX_CLK
(ports 3 and 4) is no more than 100 ps.
Parameter/Condition
Table 26. FIFO Mode Transmit AC Timing Specification
Table 27. FIFO Mode Receive AC Timing Specification
Restrictions.”
DD
DD
of 3.3 V ± 5% and 2.5 V ± 5%.
of 3.3 V ± 5% and 2.5 V ± 5%.
NOTE
t
Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management
Symbol
FIRH
t
t
t
t
t
t
FIRDV
FIRDX
t
FIR
FIRR
FIRF
FIR
FIRJ
Symbol
t
FITH/
Table 26
t
t
/t
t
FITDX
t
FITDV
t
t
FITR
t
FITF
1
FITJ
1
FIR
FIT
FIT
t
FIT
and
Min
7.0
5.3
1.5
0.5
45
—
—
—
Min
7.0
5.3
2.0
0.5
45
—
—
—
Table
27.
Typ
8.0
8.0
50
—
—
—
—
—
Typ
8.0
8.0
50
—
—
—
—
—
Max
0.75
0.75
100
100
250
Max
0.75
0.75
100
100
250
55
3.0
—
—
55
—
Unit
Unit
ns
ns
ps
ns
ns
ns
ns
%
ns
ns
ps
ns
ns
ns
ns
%
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