mpc8641 Freescale Semiconductor, Inc, mpc8641 Datasheet - Page 49
mpc8641
Manufacturer Part Number
mpc8641
Description
Integrated Host Processor Hardware Specifications
Manufacturer
Freescale Semiconductor, Inc
Datasheet
1.MPC8641.pdf
(130 pages)
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Freescale Semiconductor
LA[27:31]/LBCTL/LBCKE/LOE/
Internal launch/capture clock
LSDA10/LSDWE/LSDRAS/
Output (Address) Signal:
LSDCAS/LSDDQM[0:3]
Output (Data) Signals:
LAD[0:31]/LDP[0:3]
LAD[0:31]/LDP[0:3]
Output Signals:
MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 2
Input Signals:
In PLL bypass mode, LCLK[n] is the inverted version of the internal clock
with the delay of
of the internal clock and are captured at falling edge of the internal clock,
with the exception of the LGTA/LUPWAIT signal, which is captured at the
rising edge of the internal clock.
Input Signal:
LUPWAIT
LAD[0:31]
LCLK[n]
LGTA
LALE
Figure 27. Local Bus Signals (PLL Bypass Mode)
t
LBKHKT.
In this mode, signals are launched at the rising edge
t
LBKLOV1
t
LBKLOV2
NOTE
t
t
LBKLOV3
LBKLOV4
t
LBKHKT
t
LBIVKH1
t
LBOTOT
t
t
LBKLOX1
LBKLOX2
t
LBIXKH1
t
LBIVKL2
t
LBIXKL2
Local Bus
t
t
LBKLOZ1
LBKLOZ2
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