mpc8640 Freescale Semiconductor, Inc, mpc8640 Datasheet

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... MPC8640D are noted. Figure 1 shows the major functional units within the MPC8640 and MPC8640D. The major difference between the MPC8640 and MPC8640D is that there are two cores on the MPC8640D. © Freescale Semiconductor, Inc., 2009. All rights reserved. Document Number: MPC8640DEC Rev ...

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... Controller MII, RGMII, TBI, RTBI 10/100/1Gb Enhanced TSEC RMII, GMII, Controller MII, RGMII, TBI, RTBI 10/100/1Gb MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev 1-Mbyte L2 Cache 32-Kbyte L1 Instruction Cache MPX Bus MPX Coherency Module (MCM) Platform Bus Serial RapidIO ...

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... Four outbound windows plus default translation for PCI Express interface unit — Eight outbound windows plus default translation for serial RapidIO® interface unit with segmentation and subsegmentation support MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3 Freescale Semiconductor Overview ...

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... Programming model is compliant with the OpenPIC architecture — Supports 16 programmable interrupt and processor task priority levels — Supports 12 discrete external interrupts and 48 internal interrupts — Eight global high resolution timers/counters that can generate interrupts MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev Freescale Semiconductor ...

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... Programming model compatible with the original 16450 UART and the PC16550D • IEEE 1149.1™-compliant, JTAG boundary scan • Available as 1023 pin Hi-CTE flip chip ceramic ball grid array (FC-CBGA) MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3 Freescale Semiconductor 2 C addressing mode Overview ...

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... I/O supply voltage eTSEC 3 and 4 I/O supply voltage Local Bus, DUART, DMA, Multiprocessor Interrupts, System Control & Clocking, Debug, Test, Power management, I JTAG and Miscellaneous I/O voltage MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev Table 1. Absolute Maximum Ratings Symbol V ...

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... Stresses beyond those listed may affect device reliability or cause permanent damage to the device. 2. Core 1 characteristics apply only to MPC8640D. If two separate power supplies are used for V they must be kept within 100 mV of each other during normal run time. ...

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... This voltage is the input to the filter discussed in the voltage at the AV _Core n pin, which may be reduced from V DD 12. Applies to part number MC8640DTxxyyyyaz. Refer to has been marked for extended operating temperature range. MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev Symbol V _PLAT DD ...

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... Figure 2 shows the undershoot and overshoot voltages at the interfaces of the MPC8640. L/T/D n _G/O/X/SV L/T/D n _G/O/X/SV L/T/D n _G/O/X/ Note references clocks for various functional blocks as follows: CLK DDRn = 10% of Dn_MCK period eTSECn = 10% of ECn_GTX_CLK125 period Local Bus = 10% of LCLK[0:2] period I2C = 10% of SYSCLK JTAG = 10% of SYSCLK Figure 2 ...

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... Low Voltage Transistor-Transistor Logic (LVTTL) type pins. 7. Open Drain type pins. 8. Low Voltage Differential Signaling (LVDS) type pins. 9. The drive strength of the DDR interface in half strength mode MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev Table 3. Output Drive Capability Programmable Output Impedance (Ω ...

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... Power-Up/Down Sequence The MPC8640 requires its power rails to be applied in a specific sequence to ensure proper device operation. The recommended maximum ramp up time for power supplies is 20 milliseconds. The chronological order of power up is: 1. All power rails other than DDR I/O (Dn_GV There is no required order sequence between the individual rails for this item (# 1) ...

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... SYSCLK must be driven only AFTER the power for the various power supplies is stable device sleep mode, the reset configuration signals for DRAM types (TSEC2_TXD[4],TSEC2_TX_ER) must be valid BEFORE HRESET is asserted. Figure 3. MPC8640 Power-Up and Reset Sequence MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev L/TV =2 ...

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... These power numbers are for Part Number MC8640Dwxx1067Nz and MC8640wxx1067Nz only _PLAT = 1. The power dissipation for individual power supplies of the MPC8640D is shown in Table 5. MPC8640D Individual Supply Maximum Power Dissipation Component Description Per Core voltage Supply Per Core PLL voltage supply ...

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... JTAG and miscellaneous I/O voltage. 5. Power numbers with V _Core n = 0.95 V and The maximum power supply number for the I/Os are estimates. The power dissipation for the MPC8640 single core device is shown in Table 6. MPC8640 Power Dissipation (Single Core) Core Frequency Power Mode (MHz) ...

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... Note that the symbol this case, represents the OV IN 4.1 System Clock Timing Table 8 provides the system clock (SYSCLK) AC timing specifications for the MPC8640. At recommended operating conditions (see Parameter SYSCLK frequency SYSCLK cycle time SYSCLK rise and fall time MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3 ...

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... MPC8640 input cycle-to-cycle jitter requirement. Frequency modulation and spread are separate concerns, and the MPC8640 is compatible with spread spectrum sources if the recommendations listed in observed. ...

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... The MPX platform clock frequency must be considered for proper operation of the high-speed PCI Express and Serial RapidIO interfaces as described below. For proper PCI Express operation, the MPX clock frequency must be greater than or equal to: MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3 Freescale Semiconductor . There is no minimum RTC frequency; RTC may be ...

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... PLL lock times. Parameter (Platform and E600) PLL lock times Local bus PLL Notes: 1.The PLL lock time for e600 PLLs require an additional 255 MPX_CLK cycles. MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev Min 100 3 100 ...

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... Table 14. DDR2 SDRAM Capacitance for D n _GV Parameter Input/output capacitance: DQ, DQS, DQS Delta input/output capacitance: DQ, DQS, DQS Note: 1. This parameter is sampled _GV V = 0.2 V. OUT(peak-to-peak) MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3 Freescale Semiconductor (typ) = 2.5 V and DDR2 SDRAM Symbol Min D n _GV 1.71 DD 0.49 × ...

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... MV Table 17. Current Draw Characteristics for MV Parameter Current draw for MV REF must be able to supply up to 500 μA current. 1. The voltage regulator for MV REF MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev Symbol Min D n _GV 2.375 DD 0.49 × _GV ...

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... MDQS[n]. This should be subtracted from the total timing budget. 2. The amount of skew that can be tolerated from MDQS to a corresponding MDQ signal is called t determined by the following equation: t absolute value CISKEW 3. Maximum DDR1 frequency is 400 MHz. MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3 Freescale Semiconductor Table 2) Symbol Min V — ...

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... MCK duty cycle ADDR/CMD output setup with respect to MCK ADDR/CMD output hold with respect to MCK MCS[n] output setup with respect to MCK MCS[n] output hold with respect to MCK MCK to MDQS Skew MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev MCK D0 D1 ...

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... Per the JEDEC spec the DDR2 duty cycle at 400 and 533 MHz is the low and high cycle time values. For the ADDR/CMD setup and hold specifications in assumed that the Clock Control register is set to adjust the memory clocks by 1/2 applied cycle. MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3 Freescale Semiconductor Table 2). ...

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... MDQS Figure 6 shows the DDR SDRAM output timing diagram. MCK[n] MCK[n] ADDR/CMD Write A0 MDQS[n] MDQ[x] Figure 6. DDR SDRAM Output Timing Diagram MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev MCK t DDKHMHmax DDKHMH(min) = –0.6 ns Figure 5. Timing Diagram for tDDKHMH t ...

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... Figure 7 provides the AC test load for the DDR bus. Output 7 DUART This section describes the DC and AC electrical specifications for the DUART interface of the MPC8640. 7.1 DUART DC Electrical Characteristics Table 22 provides the DC electrical characteristics for the DUART interface. Table 22. DUART DC Electrical Characteristics Parameter ...

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... Input high voltage Input low voltage Input high current ( MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev and Table 25. The potential applied to the input of a GMII, MII, TBI, into a GMII receiver powered from a 2.5-V supply). OH Symbol Min LV 3.135 DD ...

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... That is, the transmit clock must be applied to the eTSECn’s TSECn_TX_CLK, while the receive clock must be applied to pin TSECn_RX_CLK. The eTSEC internally uses the transmit MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3 Freescale Semiconductor Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management ...

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... RX_CLK duty cycle RX_CLK peak-to-peak jitter Rise time RX_CLK (20%–80%) Fall time RX_CLK (80%–20%) RXD[7:0], RX_DV, RX_ER setup time to RX_CLK RXD[7:0], RX_DV, RX_ER hold time to RX_CLK MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev Restrictions.” NOTE Table 26 and of 3.3 V ± ...

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... Parameter GMII data TXD[7:0], TX_ER, TX_EN setup time GTX_CLK to GMII data TXD[7:0], TX_ER, TX_EN delay GTX_CLK data clock rise time (20%–80%) MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3 Freescale Semiconductor Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management Figure 8 and Figure 9 ...

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... At recommended operating conditions with L/TV Parameter RX_CLK clock period RX_CLK duty cycle RXD[7:0], RX_DV, RX_ER setup time to RX_CLK RXD[7:0], RX_DV, RX_ER hold time to RX_CLK RX_CLK clock rise time (20%–80%) MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev 3.3 V ± 5% and 2.5 V ± 5%. DD Symbol 2 t ...

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... RX_CLK RXD[7:0] RX_DV RX_ER 8.2.3 MII AC Timing Specifications This section describes the MII transmit and receive AC timing specifications. MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3 Freescale Semiconductor Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management of 3.3 V ± 5% and 2.5 V ± 5 Symbol ...

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... MII receive AC timing specifications. Table 31. MII Receive AC Timing Specifications At recommended operating conditions with L/TV Parameter RX_CLK clock period 10 Mbps RX_CLK clock period 100 Mbps RX_CLK duty cycle MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev 3.3 V ± 5 Symbol 2 ...

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... MII receive AC timing diagram. RX_CLK RXD[3:0] RX_DV RX_ER 8.2.4 TBI AC Timing Specifications This section describes the TBI transmit and receive AC timing specifications. MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3 Freescale Semiconductor Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management of 3.3 V ± 5 Symbol t ...

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... TBI (T) transmit (TX) clock. For rise and fall times, the latter convention is used with the appropriate TTX letter: R (rise (fall). 2. Guaranteed by design. MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev 3.3 V ± 5% and 2.5 V ± 5 Symbol ...

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... R (rise (fall). For symbols representing skews, the subscript is skew (SK) followed by the clock that is being skewed (TRX). 2. Guaranteed by design. 3. ±100 ppm tolerance on PMA_RX_CLK[0:1] frequency MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3 Freescale Semiconductor Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management t ...

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... RX_CLK peak-to-peak jitter Rise time RX_CLK (20%–80%) Fall time RX_CLK (80%–20%) RCG[9:0] setup time to RX_CLK rising edge RCG[9:0] hold time to RX_CLK rising edge 1 ±100 ppm tolerance on RX_CLK frequency MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev TRX t t TRXH ...

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... Guaranteed by characterization 6. ±100 ppm tolerance on RX_CLK frequency. MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3 Freescale Semiconductor Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management Figure 18 ...

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... Table 36. RMII Transmit AC Timing Specifications At recommended operating conditions with L/TV Parameter REF_CLK clock period REF_CLK duty cycle REF_CLK peak-to-peak jitter Rise time REF_CLK (20%–80%) Fall time REF_CLK (80%–20%) MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev RGTH t SKRGT TXD[8:5] TXD[3:0] ...

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... REF_CLK peak-to-peak jitter Rise time REF_CLK (20%–80%) Fall time REF_CLK (80%–20%) RXD[1:0], CRS_DV, RX_ER setup time to REF_CLK rising edge MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3 Freescale Semiconductor Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management of 3.3 V ± 5%. ...

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... The electrical characteristics specified here apply to MII management interface signals MDIO (management data input/output) and MDC (management data clock). The electrical characteristics for GMII, RGMII, RMII, TBI and RTBI are specified in Ethernet (eTSEC), MII Management.” MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev 3.3 V ± 5%. DD ...

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... MDC clock pulse width high MDC to MDIO valid MDC to MDIO delay MDIO to MDC setup time MDIO to MDC hold time MDC rise time MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3 Freescale Semiconductor Ethernet Management Interface Electrical Characteristics Table 38. Symbol Min OV 3 ...

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... Output will see a 50 Ω load since what it sees is the transmission line. Figure 24 shows the MII management AC timing diagram. MDC MDIO (Input) MDIO (Output) Figure 24. MII Management Interface Timing Diagram MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev 3.3 V ± 5 Symbol Min t — ...

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... Local Bus This section describes the DC and AC electrical specifications for the local bus interface of the MPC8640. 10.1 Local Bus DC Electrical Characteristics Table 40 provides the DC electrical characteristics for the local bus interface operating at OV DC. Table 40. Local Bus DC Electrical Characteristics (3.3 V DC) Parameter High-level input voltage ...

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... Maximum possible clock skew between a clock LCLK[m] and a relative clock LCLK Skew measured between ÷ 2. complementary signals Guaranteed by design. Figure 25 provides the AC test load for the local bus. Output MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev 3.3 V)—PLL Enabled (continued) DD Symbol t LBKHOX1 t ...

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... Local bus duty cycle Internal launch/capture clock to LCLK delay Input setup to local bus clock (except LGTA/LUPWAIT) LGTA/LUPWAIT input setup to local bus clock Input hold from local bus clock (except LGTA/LUPWAIT) MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3 Freescale Semiconductor t LBIVKH1 t ...

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... LALE and any change in LAD LBOTOT 7. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered through the component pin is less than or equal to the leakage current specification. 8. Guaranteed by characterization. MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev Symbol t ...

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... LGTA/LUPWAIT signal, which is captured at the rising edge of the internal clock. MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3 Freescale Semiconductor t LBKHKT ...

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... UPM Mode Input Signal: LUPWAIT Input Signals: LAD[0:31]/LDP[0:3] UPM Mode Output Signals: LCS[0:7]/LBS[0:3]/LGPL[0:5] Figure 28. Local Bus Signals, GPCM/UPM Signals for LCRR[CLKDIV (clock ratio of 4) (PLL Enabled) MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev LBKHOV1 LBKHOZ1 t ...

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... UPM Mode Input Signal: LUPWAIT Input Signals: LAD[0:31]/LDP[0:3] UPM Mode Output Signals: LCS[0:7]/LBS[0:3]/LGPL[0:5] Figure 29. Local Bus Signals, GPCM/UPM Signals for LCRR[CLKDIV (clock ratio of 4) MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3 Freescale Semiconductor t LBKLOV1 t LBIVKH1 (PLL Bypass Mode) ...

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... UPM Mode Input Signal: LUPWAIT Input Signals: LAD[0:31]/LDP[0:3] UPM Mode Output Signals: LCS[0:7]/LBS[0:3]/LGPL[0:5] Figure 30. Local Bus Signals, GPCM/UPM Signals for LCRR[CLKDIV (clock ratio 16) MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev LBKHOV1 LBKHOZ1 t ...

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... LUPWAIT Input Signals: LAD[0:31]/LDP[0:3] UPM Mode Output Signals: LCS[0:7]/LBS[0:3]/LGPL[0:5] Figure 31. Local Bus Signals, GPCM/UPM Signals for LCRR[CLKDIV (clock ratio 16) MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3 Freescale Semiconductor t LBKLOV1 t LBIVKH1 (PLL Bypass Mode) ...

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... JTAG external clock pulse width measured at 1.4 V JTAG external clock rise and fall times TRST assert time Input setup times: Boundary-scan data Input hold times: Boundary-scan data Valid times: Boundary-scan data MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev Symbol Min –0.3 ...

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... Output Figure 32. AC Test Load for the JTAG Interface Figure 33 provides the JTAG clock input timing diagram. JTAG External Clock Figure 33. JTAG Clock Input Timing Diagram MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3 Freescale Semiconductor Table 3). 2 Symbol t JTKLDX ...

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... Parameter Input high voltage level Input low voltage level Low level output voltage Pulse width of spikes which must be suppressed by the input filter MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev TRST VM = Midpoint Voltage (OV DD /2) Figure 34. TRST Timing Diagram ...

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... Set-up time for STOP condition Bus free time between a STOP and START condition Noise margin at the LOW level for each connected device (including hysteresis) MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3 Freescale Semiconductor Electrical Characteristics (continued) of 3.3 V ± 5%. ...

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... For rise and fall times, the latter convention is used with the appropriate letter: R (rise (fall transmitter, the MPC8640 provides a delay time of at least 300 ns for the SDA signal (referred to the Vihmin of the SCL signal) to bridge the undefined region of the falling edge of SCL to avoid unintended generation of Start or Stop condition. ...

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... I2SXKL S 13 High-Speed Serial Interfaces (HSSI) The MPC8640D features two Serializer/Deserializer (SerDes) interfaces to be used for high-speed serial interconnect applications. The SerDes1 interface is dedicated for PCI Express data transfers. The SerDes2 can be used for PCI Express and/or serial RapidIO data transfers. ...

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... Since the differential output signal of the transmitter and the differential input signal of the receiver each range from A – –(A – B) volts, the peak-to-peak value of the differential transmitter output signal or the differential receiver input MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev Differential Swing, VID or VOD = A – B Differential Peak Voltage, VDIFFp = | Differential Peak-Peak Voltage, VDIFFpp = 2 × ...

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... SerDes lanes. The SerDes reference clocks inputs are SDn_REF_CLK and SDn_REF_CLK for PCI Express and Serial RapidIO. The following sections describe the SerDes reference clock requirements and some application information. MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3 Freescale Semiconductor = 2 × × |(A – B)| volts, which is twice of differential swing in ...

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... The input amplitude requirement — This requirement is described in detail in the following sections _REF_CLK SD n _REF_CLK Figure 39. Receiver of SerDes Reference Clocks MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev SRDSn are specified in Table 1 DD_ 50 W Input Amp ...

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... DC Level Requirement for SerDes Reference Clocks The DC level requirement for the MPC8640D SerDes reference clock inputs is different depending on the signaling mode used to connect the clock driver chip and SerDes reference clock inputs as described below. • Differential Mode — The input amplitude of the differential clock must be between 400 mV and 1600 mV differential peak-peak (or between 200 mV and 800 mV differential peak) ...

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... LVPECL outputs can produce signal with too large amplitude. It may need to be DC-biased at clock driver output first and followed with series attenuation resistor to reduce the amplitude, in addition to AC-coupling. MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev Vmax < Vcm + 400 mV Vcm Vmin > ...

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... Figure 43 shows the SerDes reference clock connection reference circuits for HCSL type clock driver. It assumes that the DC levels of the clock driver chip is compatible with MPC8640D SerDes reference clock input’s DC requirement. Figure 43–Figure 46 differences in the clock driver chip’s internal structure, output impedance, ...

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... R2 is used together with the SerDes reference clock receiver’s 50-Ω termination resistor to attenuate the LVPECL output’s differential peak level such that it meets the MPC8640D SerDes reference clock’s differential input amplitude requirement (between 200 mV and 800 mV differential peak). For example, if the LVPECL output’ ...

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... Figure 45. AC-Coupled Differential Connection with LVPECL Clock Driver (Reference Only) Figure 46 shows the SerDes reference clock connection reference circuits for a single-ended clock driver. It assumes the DC levels of the clock driver are compatible with MPC8640D SerDes reference clock input’s DC requirement. Single-Ended CLK Driver Chip 33 Ω ...

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... –200 _REF_CLK minus SD n _REF_CLK Figure 47. Differential Measurement Points for Rise and Fall Time MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev SRDS1 or XV SRDS2 = 1.1 V ± 5% and 1.05 V ± 5%. DD_ DD_ Symbol Rise Edge Rate Fall Edge Rate ...

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... Section 15, “Serial RapidIO” Note that external AC Coupling capacitor is required for the above two serial transmission protocols with the capacitor value defined in specification of each protocol section. MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3 Freescale Semiconductor SD n _REF_CLK SD n _REF_CLK ...

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... PCI Express 14 PCI Express This section describes the DC and AC electrical specifications for the PCI Express bus of the MPC8640. 14.1 DC Requirements for PCI Express SD n _REF_CLK and SD n _REF_CLK For more information, see Section 13.2, “SerDes Reference Clocks.” 14.2 AC Requirements for PCI Express SerDes Clocks Table 48 lists AC requirements ...

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... TX-DC-CM Common Mode Voltage Tx Short Circuit I TX-SHORT Current Limit Minimum time T TX-IDLE-MIN spent in electrical idle MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3 Freescale Semiconductor Min Nom Max Units –3.0 –3.5 –4.0 dB Ratio of the V after a transition divided by the V bit after a transition. See Note 2. ...

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... Measured between 20–80% at transmitter package pins into a test load as shown in 6. See Section 4.3.1.8 of the PCI Express Base Specifications Rev 1.0a 7. See Section 4.2.6.3 of the PCI Express Base Specifications Rev 1.0a 8. MPC8640D SerDes transmitter does not have C MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev Min Nom ...

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... UI interval with a fit algorithm using a minimization merit function (that is, least squares and median deviation fits). Figure 50. Minimum Transmitter Timing and Voltage Output Compliance Specifications MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3 Freescale Semiconductor is specified using the passive compliance/test measurement load (see ...

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... Return Loss DC Differential Z RX-DIFF-DC Input Impedance DC Input Z RX-DC Impedance Powered Down Z RX-HIGH-IMP-DC DC Input Impedance Electrical Idle V RX-IDLE-DET-DIFFp-p Detect Threshold MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev Min Nom Max Units 399.88 400 400.12 ps 0.175 — 1.200 V 0.4 — — UI — ...

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... PCI Express component to vary in impedance from the compliance/test measurement load. The input receiver eye diagram is implementation specific and is not specified component designer should provide MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3 Freescale Semiconductor Min ...

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... D+ and D– line (that is, as measured by a vector network analyzer Ω with 50- probes—see optional for the return loss measurement. Figure 51. Minimum Receiver Eye Timing and Voltage Compliance Specification MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev NOTE Figure 52). Note that the series capacitors, C Ω ...

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... Figure 52. Compliance Test/Measurement Load 15 Serial RapidIO This section describes the DC and AC electrical specifications for the RapidIO interface of the MPC8640, for the LP-Serial physical layer. The electrical specifications cover both single and multiple-lane links. Two transmitter types (short run and long run single receiver are specified for each of three baud rates, 1 ...

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... The differential input signal of the receiver The differential output signal of the transmitter and the differential input signal of the receiver each range from A – –(A – B) volts MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev Min Typical Max Units — ...

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... XAUI has similar application goals to the serial RapidIO interface. The goal of this standard is that electrical designs for the serial RapidIO interface can reuse electrical designs for XAUI, suitably modified for applications at the baud intervals and reaches described herein. MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3 Freescale Semiconductor Differential Peak-Peak = 2 * (A-B) ...

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... Deterministic Jitter Total Jitter Multiple output skew Unit Interval Table 53. Short Run Transmitter AC Timing Specifications—2.5 GBaud Parameter Output Voltage Differential Output Voltage Deterministic Jitter Total Jitter MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev Range Symbol Min Max V –0.40 2.30 O ...

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... TC: What was this? Was there a figure here? Table 55. Long Run Transmitter AC Timing Specifications—1.25 GBaud Parameter Output Voltage, Differential Output Voltage Deterministic Jitter Total Jitter Multiple output skew Unit Interval MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3 Freescale Semiconductor Range Symbol Min Max S — 1000 ...

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... This figure should be used with the parameters specified in output pins of the device and the device is driving a 100-Ω ± 5% differential resistive load. The output eye pattern of an LP-Serial transmitter that implements pre-emphasis (to equalize the link and reduce MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev Range ...

Page 81

... Receiver input impedance shall result in a differential return loss better that 10 dB and a common mode return loss better than 6 dB from 100 MHz to (0.8) × (Baud Frequency). This includes contributions from on-chip circuitry, the chip package and any off-chip components related to the receiver. AC-coupling MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3 Freescale Semiconductor A ...

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... Total jitter is composed of three components, deterministic jitter, random jitter and single frequency sinusoidal jitter. The sinusoidal jitter may have any amplitude and frequency in the unshaded region of is included to ensure margin for low frequency jitter, wander, noise, crosstalk and other variable system effects. MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev Range ...

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... Total jitter is composed of three components, deterministic jitter, random jitter and single frequency sinusoidal jitter. The sinusoidal jitter may have any amplitude and frequency in the unshaded region of is included to ensure margin for low frequency jitter, wander, noise, crosstalk, and other variable system effects. MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3 Freescale Semiconductor Range ...

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... Serial RapidIO Figure 55 shows the single frequency sinusoidal jitter limits. 8.5 UI p-p Sinusoidal Jitter Amplitude 0.10 UI p-p 22.1 kHz Figure 55. Single Frequency Sinusoidal Jitter Limits MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev 1.875 MHz 20 MHz Frequency Freescale Semiconductor ...

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... Table 62. Receiver Input Compliance Mask Parameters Exclusive of Sinusoidal Jitter Receiver Type 1.25 GBaud 2.5 GBaud 3.125 GBaud MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3 Freescale Semiconductor (Table 59 through Table Table 62 ...

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... Eye template measurement requirements are as defined above. MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev Section 15.7, “Receiver Specifications,” ...

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... Maximum module height Minimum module height Solder Balls 2 Ball diameter (typical ) 1 High-coefficient of thermal expansion 2 Typical ball diameter is before reflow MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3 Freescale Semiconductor Section 15.7, “Receiver 12.1 mm × 14 × 1023 caps; 100 nF each 1 HX) 2 ...

Page 88

... Package 16.2 Mechanical Dimensions of the MPC8640 FC-CBGA The mechanical dimensions and bottom surface nomenclature of the MPC8640D (dual core) and MPC8640 (single core) high-lead FC-CBGA (package option: HCTE HX) and lead-free FC-CBGA (package option: HCTE VU) are shown respectfully in Figure 57. MPC8640D High-Lead FC-CBGA Dimensions MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3 ...

Page 89

... All dimensions symmetrical about centerlines unless otherwise specified. 8. Note that for MPC8640 (single core) the solder balls for the following signals/pins are not populated in the package: VDD_Core1 (R16, R18, R20, T17, T19, T21, T23, U16, U18, U22, V17, V19, V21, V23, W16, W18, W20, W22, Y17, Y19, Y21, Y23, AA16, AA18, AA20, AA22, AB23, AC24) and SENSEVDD_Core1 (U20) ...

Page 90

... Package Figure 58. MPC8640D Lead-Free FC-CBGA Dimensions MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev Freescale Semiconductor ...

Page 91

... All dimensions symmetrical about centerlines unless otherwise specified. 8. Note that for MPC8640 (single core) the solder balls for the following signals/pins are not populated in the package: VDD_Core1 (R16, R18, R20, T17, T19, T21, T23, U16, U18, U22, V17, V19, V21, V23, W16, W18, W20, W22, Y17, Y19, Y21, Y23, AA16, AA18, AA20, AA22, AB23, AC24) and SENSEVDD_Core1 (U20) ...

Page 92

... L26, M24, N26, P24, R26, T24, U26, V24 SD1_TX[0:7] L27, M25, N27, P25, R27, T25, U27, V25 SD1_RX[0:7] J32, K30, L32, M30, T30, U32, V30, W32 MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev Package Pin Number DDR Port 1 DDR Memory Interface 2 Signals ...

Page 93

... AD26 Reserved H30, R32, V28, AG32 Reserved H29, R31, W28, AG31 Reserved AD24, AG26 MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3 Freescale Semiconductor Package Pin Number High Speed I/O Interface 2 (SERDES 2) Special Connection Requirement pins Ethernet Miscellaneous Signals Signal Listings ...

Page 94

... AE20 TSEC2_COL AE21 TSEC2_RXD[0:7]/ AL22, AK22, AM21, AH20, AG20, AF20, GPIN[8:15] AF23, AF22 TSEC2_RX_DV AC19 TSEC2_RX_ER AD21 MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev Package Pin Number 5 eTSEC Port 1 Signals 5 eTSEC Port 2 Signals Pin Type Power Supply I LV ...

Page 95

... TSEC4_RXD[0:7] AG14, AD13, AF13, AD14, AE14, AB15, AC14, AE17 TSEC4_RX_DV AC15 TSEC4_RX_ER AF14 TSEC4_RX_CLK AG13 MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3 Freescale Semiconductor Package Pin Number 5 eTSEC Port 3 Signals 5 eTSEC Port 4 Signals Signal Listings Pin Type Power Supply ...

Page 96

... DMA_DREQ[0:1] E31, E32 DMA_DREQ[2]/LCS[5] B23 DMA_DREQ[3]/IRQ[9] B30 DMA_DACK[0:1] D32, F30 DMA_DACK[2]/LCS[6] E23 DMA_DACK[3]/IRQ[10] C30 MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev Package Pin Number 5 Local Bus Signals 5 DMA Signals Pin Type Power Supply I ...

Page 97

... SMI_1 L16 SRESET_0 C20 SRESET_1 C21 CKSTP_IN L18 CKSTP_OUT L17 READY/TRIG_OUT J13 MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3 Freescale Semiconductor Package Pin Number Programmable Interrupt Controller Signals 5 DUART Signals Signals System Control Signals Signal Listings Pin Type ...

Page 98

... GPIN[0:7]/ AL25, AL24, AK26, AK25, AM26, AF26, TSEC1_RXD[0:7] AH24, AG25 GPOUT[8:15]/ AB20, AJ23, AJ22, AD19, AH23, AH21, TSEC2_TXD[0:7] AG22, AG21 MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev Package Pin Number 5 Debug Signals Power Management Signals System Clocking Signals 5 ...

Page 99

... F26, F29, G17, H21, H24, K19, K23, M21, AM30 LV AC20, AD23, AH22 DD TV AC17, AG18, AK20 DD MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3 Freescale Semiconductor Package Pin Number Additional Analog Signals Sense, Power and GND Signals V DD sensing pin ...

Page 100

... DD AV _LB A20 DD AV _SRDS1 P32 DD AV _SRDS2 AF32 DD MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3 100 Package Pin Number Transceiver Power Supply Power Supply for SerDes Power Supply for SerDes Core 0 voltage Core 1 voltage Platform supply Core 0 PLL ...

Page 101

... AE22, AD22 cfg_tsec1_prtcl[0:1] TSEC2_TXD[0:3]/ AB20, AJ23, AJ22, AD19 cfg_rom_loc[0:3] TSEC2_TXD[4], AH23, TSEC2_TX_ER/ AB19 cfg_dram_type[0:1] MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3 Freescale Semiconductor Package Pin Number SerDes Port 1 Ground pin for AV SerDes Port 2 Ground pin for AV Ground pins for ...

Page 102

... J21 LA[28:31]/ K21, G22, F24, G21 cfg_sys_pll[0:3] LGPL[3], K20, LGPL[5]/ J19 cfg_boot_seq[0:1] D1_MSRCID[0]/ F15 cfg_mem_debug D1_MSRCID[1]/ K15 cfg_ddr_debug MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3 102 Package Pin Number Pin Type Power Supply — — — ...

Page 103

... Used as serial data input for serial RapidIO 1×/4× link. 36.This pin requires an external 4.7-kΩ pull-down resistor to prevent PHY from seeing a valid transmit enable before it is actively driven. MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3 Freescale Semiconductor Package Pin Number ...

Page 104

... S3 . This pin should be pulled to GND for the single core device special requirement for this pin on single core device. Pin should be tied to power supply as directed for dual core. 18 Clocking This section describes the PLL configuration of the MPC8640. Note that the platform clock is identical to the MPX clock. 18.1 ...

Page 105

... The MPX clock is the clock that drives the MPX bus, and is also called the platform clock. The frequency of the MPX is set using the following reset signals, as shown in • SYSCLK input signal MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3 Freescale Semiconductor Maximum Processor Core Frequency ...

Page 106

... LDP[0:3], LA[27](cfg_core_pll[0:4] - reset config name) at power up, as shown in Table 69. LDP[0:3], LA[27] Signals 18.4 Frequency Options This section discusses the frequency options for the MPC8640. MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3 106 Table 68. MPX:SYSCLK Ratio Binary Value of MPX:SYSCLK Ratio LA[28:31] Signals 0000 ...

Page 107

... For example, if the platform frequency is 500 MHz, the FIFO Tx/Rx clock frequency should be no more than 156 MHz. 19 Thermal This section describes the thermal specifications of the MPC8640. MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3 Freescale Semiconductor Section 17, “Signal Listings,” SYSCLK (MHz) ...

Page 108

... This section provides thermal management information for the high coefficient of thermal expansion (HCTE) package for air-cooled applications. Proper thermal control design is primarily dependent on the system-level design—the heat sink, airflow, and thermal interface material. The MPC8640 implements several features designed to assist with thermal management, including the temperature diode. The temperature diode allows an external device to monitor the die temperature in order to detect excessive temperature conditions and alert the system ...

Page 109

... Occasionally the spring clip is attached to soldered hooks plastic backing structure. Screw and spring arrangements are also frequently used. Interface Material Figure 59. FC-CBGA Package Exploded Cross-Sectional View with Several Heat Sink Options There are several commercially-available heat sinks for the MPC8640 provided by the following vendors: Aavid Thermalloy 80 Commercial St. Concord, NH 03301 Internet: www ...

Page 110

... External Resistance Internal Resistance External Resistance (Note the internal versus external package resistance.) Figure 60. C4 Package with Heat Sink Mounted to a Printed-Circuit Board MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3 110 408-436-8770 800-522-6752 603-635-5102 Table 71, the intrinsic conduction thermal ...

Page 111

... Figure 59). Therefore, synthetic grease offers the best thermal performance, considering the low interface pressure, and is recommended due to the high power dissipation of the MPC8640. Of course, the selection of any thermal interface material depends on many factors—thermal performance requirements, manufacturability, service temperature, dielectric properties, cost, and so on. ...

Page 112

... R is the adhesive or interface material thermal resistance θint R is the heat sink base-to-ambient thermal resistance θ the power dissipated by the device d MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3 112 800-347-4572 781-935-4850 800-248-2481 888-642-7674 888-246-9050 ) × θ ...

Page 113

... For these reasons, we recommend using conjugate heat transfer models for the board as well as system-level designs. For system thermal modeling, the MPC8640 thermal model is shown in to represent this device. The die is modeled as 12.4 × 15 thickness of 0.86 mm. See “Power Characteristics,” ...

Page 114

... Figure 62. Recommended Thermal Model of MPC8640 19.2.4 Temperature Diode The MPC8640 has a temperature diode on the microprocessor that can be used in conjunction with other system temperature monitoring devices (such as Analog Devices, ADT7461™). These devices use the negative temperature coefficient of a diode operated at a constant current to determine the temperature of the microprocessor and its environment ...

Page 115

... The above simplifies to the following –4 = 1.986 × 10 × – Solving for T, the equation becomes: V – __________ nT = –4 1.986 × 10 MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3 Freescale Semiconductor is flowing H is flowing L –19 C) –23 Joules/K) Thermal 115 ...

Page 116

... PLL power supply filter circuits for the platform and cores, respectively. 10 Ω V _PLAT DD Figure 63. MPC8640 PLL Power Supply Filter Circuit (for platform and Local Bus) MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3 116 Section 18.2, “MPX to SYSCLK PLL Ratio.” is provided with power through independent ...

Page 117

... This noise must be prevented from reaching other components in the MPC8640 system, and the device itself requires a clean, tightly regulated source of power. Therefore recommended that the system MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev ...

Page 118

... Note that these power supplies can only be powered up again at reset for functionality to occur on the DDR port. Power supplies for other functional buses should remain powered. MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3 118 , Dn_GV ...

Page 119

... DEVDISR. See Note 1 for more information. If the high-speed SerDes port requires complete or partial termination, the unused pins should be terminated as described in this section. MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3 Freescale Semiconductor Section 20.5.1, “Guidelines for High-Speed Interface Table 72 ...

Page 120

... For other directions on reserved or no-connects pins see 20.6 Pull-Up and Pull-Down Resistor Requirements The MPC8640 requires weak pull-up resistors (2–10 kΩ is recommended) on all open drain type pins. The following pins must not be pulled down during power-on reset: TSEC4_TXD[4], LGPL0/LSDA10, LGPL1/LSDWE, TRIG_OUT/READY, and D1_MSRCID[2]. ...

Page 121

... For other pin pull-up or pull-down recommendations of signals, please see 20.7 Output Buffer DC Impedance The MPC8640 drivers are characterized over process, voltage, and temperature. For all buses, the driver is a push-pull single-ended driver type (open drain for I To measure Z for the single-ended drivers, an external resistor is connected from the chip pad GND ...

Page 122

... Configuration Pin Muxing The MPC8640 provides the user with power-on configuration options which can be set through the use of external pull-up or pull-down resistors of 4.7 kΩ on certain output pins (see customer visible configuration pins). These pins are generally used as output only pins in normal operation. ...

Page 123

... No connection is required for TDI, TMS, or TDO. COP_SRESET COP_HRESET COP_CHKSTP_OUT MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3 Freescale Semiconductor Figure 67, for connection to the target system, and is Figure 68, can be duplicated for each processor. The Figure 69 ...

Page 124

... This switch is included as a precaution for BSDL testing. The switch should be open during BSDL testing to avoid accidentally asserting the TRST line. If BSDL testing is not being performed, this switch should be closed or removed. Figure 68. JTAG/COP Interface Connection for one MPC8640 device MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3 124 COP_HRESET ...

Page 125

... Although pin 12 is defined as a No-Connect, some debug tools may use pin additional GND pin for improved signal integrity. Figure 69. JTAG/COP Interface Connection for Multiple MPC8640 Devices in Daisy Chain Configuration MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3 Freescale Semiconductor ...

Page 126

... Part Numbers Fully Addressed by This Document Table 74 provides the Freescale part numbering nomenclature for the MPC8640. Note that the individual part numbers correspond to a maximum processor core frequency. For available frequencies, contact your local Freescale sales office. In addition to the processor frequency, the part numbering scheme also includes an application modifier which may specify special application conditions ...

Page 127

... Note that the “w” represents the operating temperature range. The “xx” in the part marking represents the package option. The “z” represents the product revision level. For more information see MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3 Freescale Semiconductor ...

Page 128

... Updated Table Conditions,” to include silicon revision 3.0 part markings. 2 06/2009 • Added Table • Added Note 8 to MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3 128 Figure 70. MC8640x xxnnnnxx TWLYYWW MMMMMM YWWLAZ Table 76. Document Revision History Substantive Change(s) 74, “ ...

Page 129

... Removed the part offering MC8640Dwxx1000NC which is replaced with MC8640Dwxx1067NC and removed MC8640wxx1000NC replaced with MC8640wxx1067NC in • Added Note 07/2008 • Initial Release MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3 Freescale Semiconductor Table 76. Document Revision History Substantive Change(s) Table 2 because it is not supported by MPC8640D or MPC8640 ...

Page 130

... Literature Distribution Center 1-800 441-2447 or +1-303-675-2140 Fax: +1-303-675-2150 LDCForFreescaleSemiconductor @hibbertgroup.com Document Number: MPC8640DEC Rev. 3 07/2009 Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document ...