mpc8640 Freescale Semiconductor, Inc, mpc8640 Datasheet - Page 22

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mpc8640

Manufacturer Part Number
mpc8640
Description
Integrated Host Processor
Manufacturer
Freescale Semiconductor, Inc
Datasheet
DDR and DDR2 SDRAM
Figure 4
6.2.2
At recommended operating conditions (see
22
MCK[n] cycle time, MCK[n]/MCK[n] crossing
MCK duty cycle
ADDR/CMD output setup with respect to MCK
ADDR/CMD output hold with respect to MCK
MCS[n] output setup with respect to MCK
MCS[n] output hold with respect to MCK
MCK to MDQS Skew
MDQS[n]
MDQ[x]
shows the DDR SDRAM input timing for the MDQS to MDQ skew measurement (tDISKEW).
MCK[n]
MCK[n]
DDR SDRAM Output AC Timing Specifications
MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3
Parameter
Table 21. DDR SDRAM Output AC Timing Specifications
Figure 4. DDR Input Timing Diagram for tDISKEW
Table
533 MHz
400 MHz
533 MHz
400 MHz
533 MHz
400 MHz
533 MHz
400 MHz
533 MHz
400 MHz
2).
t
t
MCK
DISKEW
t
MCKH
Symbol
t
t
t
t
t
DDKHMH
DDKHCS
DDKHCX
DDKHAS
DDKHAX
t
MCK
/t
MCK
1
D0
1.48
1.95
1.48
1.95
1.48
1.95
1.48
1.95
–0.6
Min
47
47
D1
3
t
DISKEW
Max
0.6
10
53
53
Freescale Semiconductor
Unit
ns
ns
ns
ns
ns
ns
%
Notes
2
8
8
3
7
3
7
3
7
3
7
4

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