mpc8640 Freescale Semiconductor, Inc, mpc8640 Datasheet - Page 107

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mpc8640

Manufacturer Part Number
mpc8640
Description
Integrated Host Processor
Manufacturer
Freescale Semiconductor, Inc
Datasheet
18.4.1
Table 70
clock to SYSCLK ratio. Note that frequencies between 400 MHz and 500 MHz are not supported on the
platform. See note regarding cfg_platform_freq in
configuration pin that is related to platform frequency.
18.4.2
Please note the following FIFO maximum speed restrictions based on platform speed:
For FIFO GMII mode:
For FIFO encoded mode:
19 Thermal
This section describes the thermal specifications of the MPC8640.
Freescale Semiconductor
FIFO TX/RX clock frequency ≤ platform clock frequency ÷ 4.2
For example, if the platform frequency is 500 MHz, the FIFO Tx/Rx clock frequency should be no
more than 119 MHz.
FIFO TX/RX clock frequency ≤ platform clock frequency ÷ 3.2
For example, if the platform frequency is 500 MHz, the FIFO Tx/Rx clock frequency should be no
more than 156 MHz.
shows some SYSCLK frequencies and the expected MPX frequency values based on the MPX
Table 70. Frequency Options of SYSCLK with Respect to Platform/MPX Clock Speed
SYSCLK to Platform Frequency Options
Platform to FIFO Restrictions
MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3
1
SYSCLK
MPX to
SYSCLK frequency range is 66-167 MHz. Platform clock/MPX
frequency range is 400 MHz, 500-533 MHz.
Ratio
2
3
4
5
6
8
400
533
66
Platform/MPX Frequency (MHz)
500
83
Section 17, “Signal Listings,”
SYSCLK (MHz)
100
400
500
133
400
533
1
167
500
because it is a reset
Thermal
107

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