mpc5553 Freescale Semiconductor, Inc, mpc5553 Datasheet - Page 12

• Manufacturer Part Number: mpc5553
• Description: Mpc5553 High Performance Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

Electrical Characteristics
Table 8
pad_sh (slow type).
3.7.1
When powering up the device, V
more than the V
bypass clock mode because the internal versions of PLLCFG[0:1] and RSTCFG are not powered and
therefore cannot read the default state when POR negates. V
pin (V
applies during power up only. V
3.7.2
The 1.5 V V
power supply rises above 2.0 V. This ensures that digital logic in the PLL for the 1.5 V power supply does
not begin to operate below the specified operation range lower limit of 1.35 V. Because the internal 1.5 V
POR is disabled, the internal 3.3 V POR or the RESET power POR must hold the device in reset. Since
they can negate as low as 2.0 V, V
POR negate.
12
DDEH6
gives the pin state for the sequence cases for all pins with pad type pad_mh (medium type) and
Input Value of Pins During POR Dependent on V
Power-Up Sequence (V
DD
), but cannot lag both by more than the V
power supply must rise to 1.35 V before the 3.3 V V
DD33
V
V
V
V
V
DD
Low
DDEH
DDEH
DDEH
DDEH
2.0 V
must reach 1.35 V before V
lag specification listed in
Table 8. Power Sequence Pin Status for Medium / Slow Pads
V
Low
V
V
—
DD
DD
DD
Figure 2. Power-Up Sequence (V
DD33
MPC5553 Microcontroller Data Sheet, Rev. 2.0
DD33
Asserted
Asserted
Asserted
Negated
DD
POR
1.35 V
has no lead or lag requirements when powering down.
must be within specification before the 3.3 V POR and the RESET
must not lag the latest V
DDSYN
Pin Status for Medium and Slow Pad Output Driver
RC33
Table
and the RESET power reach 2.0 V
Grounded)
pad_mh (medium) pad_sh (slow)
DD33
6, spec 8. This avoids accidentally selecting the
High impedance (Hi-Z)
lag specification. This V
DD33
RC33
Functional
DDSYN
Low
Hi-Z
V
Grounded)
can lag V
DDSYN
DDSYN
or RESET power pin (V
and RESET Power
power supply and the RESET
DDSYN
V
DD
DD33
DD33
or the RESET power
Freescale Semiconductor
lag specification
DDEH6
) by