dp83901a National Semiconductor Corporation, dp83901a Datasheet - Page 18

• Manufacturer Part Number: dp83901a
• Description: Serial Network Interface Controller
• Manufacturer: National Semiconductor Corporation

8 0 Packet Transmission
The Local DMA is also used during transmission of a pack-
et Three registers control the DMA transfer during trans-
mission a Transmit Page Start Address Register (TPSR)
and the Transmit Byte Count Registers (TBCR0 1) When
the SNIC receives a command to transmit the packet point-
ed to by these registers buffer memory data will be moved
into the FIFO as required during transmission The SNIC will
generate and append the preamble synch and CRC fields
TRANSMIT PACKET ASSEMBLY
The SNIC requires a contiguous assembled packet with the
format shown The transmit byte count includes the Destina-
tion Address Source Address Length Field and Data It
does not include preamble and CRC When transmitting
data smaller than 46 bytes the packet must be padded to a
minimum size of 64 bytes The programmer is responsible
for adding and stripping pad bytes
TRANSMISSION
Prior to transmission the TPSR (Transmit Page Start Regis-
ter) and TBCR0 TBCR1 (Transmit Byte Count Registers)
must be initialized To initiate transmission of the packet the
TXP bit in the Command Register is set The Transmit
Status Register (TSR) is cleared and the SNIC begins to
prefetch transmit data from memory (unless the SNIC is cur-
rently receiving) If the interframe gap has timed out the
SNIC will begin transmission
CONDITIONS REQUIRED TO BEGIN TRANSMISSION
In order to transmit a packet the following three conditions
must be met
1 The Interframe Gap Timer has timed out the first 6 4 ms
2 At least one byte has entered the FIFO (This indicates
3 If a collision had been detected then before transmission
In typical systems the SNIC prefetchs the first burst of bytes
before the 6 4 ms timer expires The time during which SNIC
transmits preamble can also be used to load the FIFO
Note If carrier sense is asserted before a byte has been loaded into the
COLLISION RECOVERY
During transmission the Buffer Management logic monitors
the transmit circuitry to determine if a collision has occurred
If a collision is detected the Buffer Management logic will
reset the FIFO and restore the Transmit DMA pointers for
retransmission of the packet The COL bit will be set in the
TSR and the NCR (Number of Collisions Register) will be
incremented If 15 retransmissions each result in a collision
the transmission will be aborted and the ABT bit in the TSR
will be set
Note NCR reads as zeroes if excessive collisions are encountered
TBCR0 1
Transmit
of the Interframe Gap
that the burst transfer has been started )
the packet time must have timed out
Count
Byte
FIFO the SNIC will become a receiver
General Transmit Packet Format
Pad (If Data
Destination Address
Source Address
Type Length
Data
k
46 Bytes)
t
6 Bytes
6 Bytes
2 Bytes
46 Bytes
18
TRANSMIT PACKET ASSEMBLY FORMAT
The following diagrams describe the format for how packets
must be assembled prior to transmission for different byte
ordering schemes The various formats are selected in the
Data Configuration Register
BOS
This format is used with Series 32xxx or 808xx processors
BOS
This format is used with 680x0 type processors
BOS
This format is used with general 8-bit processors
Note All examples above will result in a transmission of a packet in order of
D15
D15
Destination Address 1
Destination Address 3
Destination Address 5
Destination Address 0
Destination Address 2
Destination Address 4
e
e
e
DA0 DA1 DA3
significant bit first
DA
Source Address 1
Source Address 3
Source Address 5
Source Address 0
Source Address 2
Source Address 4
0 WTS
1 WTS
0 WTS
Type Length 1
Type Length 0
e
Destination Address
Data 1
Data 0
D1
e
e
e
1 in Data Configuration Register
1 in Data Configuration Register
0 in Data Configuration Register
Destination Address 0
Destination Address 1
Destination Address 2
Destination Address 3
Destination Address 4
Destination Address 5
Source Address 0
Source Address 1
Source Address 2
Source Address 3
Source Address 4
Source Address 5
bits within each byte will be transmitted least
D8 D7
D8 D7
Destination Address 0
Destination Address 2
Destination Address 4
Destination Address 1
Destination Address 3
Destination Address 5
Source Address 0
Source Address 2
Source Address 4
Source Address 1
Source Address 3
Source Address 5
Type Length 0
Type Length 1
Data 0
Data 1
D0
D0
D0