dp83901a National Semiconductor Corporation, dp83901a Datasheet - Page 41

• Manufacturer Part Number: dp83901a
• Description: Serial Network Interface Controller
• Manufacturer: National Semiconductor Corporation

13 0 Bus Arbitration and Timing
Threshold Detection (Bus Latency)
To assure that no overwriting of data in the FIFO occurs the
FIFO logic flags a FIFO overrun as the 13th byte is written
into the FIFO effectively shortening the FIFO to 13 bytes
The FIFO logic also operates differently in Byte Mode and in
Word Mode In Byte Mode a threshold is indicated when
the n
threshold the SNIC issues Bus Request (BREQ) when the
9th byte has entered the FIFO For Word Mode BREQ is
not generated until the n
Thus with a 4 word threshold (equivalent to 8 byte thres-
a
1 byte has entered the FIFO thus with an 8 byte
a
2 bytes have entered the FIFO
Transmit Prefetch Timing
(Continued)
41
hold) BREQ is issued when the 10th byte has entered the
FIFO The two graphs indicate the maximum allowable bus
latency for Word or Byte transfer modes
The FIFO at the Beginning of Transmit
Before transmitting the SNIC performs a prefetch from
memory to load the FIFO The number of bytes prefetched
is the programmed FIFO threshold The next BREQ is not
issued until after the SNIC actually begins transmitting data
i e after SFD The Transmit Prefetch diagram illustrates
this process
TL F 10469 – 56