dp83901a National Semiconductor Corporation, dp83901a Datasheet - Page 3

• Manufacturer Part Number: dp83901a
• Description: Serial Network Interface Controller
• Manufacturer: National Semiconductor Corporation

BUS INTERFACE PINS
Pin No
22 – 25
7 – 17
3 – 6
Pin Description
19
26
27
28
29
30
31
32
34
36
37
38
2
PRD
RA0 – RA3
AD0 – AD15
ADS0
CS
MWR
MRD
SWR
SRD
ACK
BSCK
RACK
PWR
READY
Pin Name
I O Z
I O Z
O Z
O Z
I O
O
O
O
O
I
I
I
I
I
I
PORT READ Enables data from external latch on to local bus during a memory write cycle to
local memory (remote write operation) This allows asynchronous transfer of data from the
system memory to local memory
REGISTER ADDRESS These four pins are used to select a register to be read or written The
state of these inputs is ignored when the NIC is not in slave mode (CS high)
MULTIPLEXED ADDRESS DATA BUS
ADDRESS STROBE 0
CHIP SELECT Chip Select places controller in slave mode for mP access to internal registers
Must be valid through data portion of bus cycle RA0 – RA3 are used to select the internal
register SWR and SRD select direction of data transfer
MASTER WRITE STROBE (Strobe for DMA transfers)
Active low during write cycles (t2 t3 tw) to buffer memory Rising edge coincides with the
presence of valid output data TRI-STATE until BACK asserted
MASTER READ STROBE (Strobe for DMA transfers)
Active during read cycles (t2 t3 tw) to buffer memory Input data must be valid on rising edge of
MRD TRI-STATE until BACK asserted
SLAVE WRITE STROBE Strobe from CPU to write an internal register selected by RA0 – RA3
Data is latched into the SNIC on the rising edge of this input
SLAVE READ STROBE Strobe from CPU to read an internal register selected by RA0 – RA3
The register data is output when SRD goes low
ACKNOWLEDGE Active low when SNIC grants access to CPU Used to insert WAIT states to
CPU until SNIC is synchronized for a register read or write operation
BUS CLOCK This clock is used to establish the period of the DMA memory cycle Four clock
cycles (t1 t2 t3 t4) are used per DMA cycle DMA transfers can be extended by one BSCK
increments using the READY input
READ ACKNOWLEDGE Indicates that the system DMA or host CPU has read the data placed
in the external latch by the SNIC The SNIC will begin a read cycle to update the latch
PORT WRITE Strobe used to latch data from the SNIC into external latch for transfer to host
memory during Remote Read transfers The rising edge of PWR coincides with the presence of
valid data on the local bus
READY This pin is set high to insert wait states during a DMA transfer The SNIC will sample this
signal at t3 during DMA transfers




During t1 of memory cycle AD0 – AD15 contain address
During t2 t3 t4 AD0 – AD15 contain data (word transfer mode)
During t2 t3 t4 AD0 – AD7 contain data AD8 – AD15 contain address (byte transfer mode)
Direction of transfer is indicated by SNIC on MWR MRD lines
Register Access with DMA inactive CS low and ACK returned from SNIC pins AD0–AD7 are
used to read and write register data AD8–AD15 float during I O transfers SRD SWR pins are
used to select direction of transfer
Bus Master with BACK input asserted
Input with DMA inactive and CS low latches RA0–RA3 inputs on falling edge If high data
present on RA0–RA3 will flow through latch
Output When Bus Master latches address bits (A0–A15) to external memory during DMA
transfers
3
Description