dp83901a National Semiconductor Corporation, dp83901a Datasheet - Page 52

• Manufacturer Part Number: dp83901a
• Description: Serial Network Interface Controller
• Manufacturer: National Semiconductor Corporation

15 0 Switching Characteristics
Note 1 BACK must be setup before T1 after BREQ is asserted Missed setup will slip the beginning of the DMA by four bus clocks The Bus Latency will influence
the allowable FIFO threshold and transfer mode (empty fill vs exact burst transfer)
Note 2 During remote DMA transfers only a single bus transfer is performed During local DMA operations burst mode transfers are performed
Note 3 These limits include the RC delay inherent in our test method These signals typically turn off within 15 ns enabling other devices to drive these lines with
no contention
Symbol
brqhl
brqhr
brql
backs
bccte
bcctr
Bus Clock to Bus Request High for Local DMA
Bus Clock to Bus Request High for Remote DMA
Bus Request Low from Bus Clock
Acknowledge Setup to Bus Clock (Note 1)
Bus Clock to Control Enable
Bus Clock to Control Release (Notes 2 3)
Parameter
DMA Control Bus Arbitration
AC Specs DP83901A Note All Timing is Preliminary (Continued)
52
Min
2
Max
50
45
60
60
70
TL F 10469 – 36
Units
ns
ns
ns
ns
ns
ns