adau1373 Analog Devices, Inc., adau1373 Datasheet - Page 251

• Manufacturer Part Number: adau1373
• Description: Low Power Codec With Speaker And Headphone Amplifier Adau1373
• Manufacturer: Analog Devices, Inc.

ALC_CTRL6 REGISTER
Address: 0xC8, Reset: 0x00, Name: ALC_CTRL6
ALC Control Register
Table 223. Bit Descriptions for ALC_CTRL6
Bits
7
6
[5:4]
[3:2]
[1:0]
Bit Name
HLDRST
ALCHPF
NGMODE
ALCEN
ALCMODE
Settings
00
01
10
11
00
01
10
11
00
01
10
11
1
0
1
0
Description
Recovery Hold Time Counter Clear Control. Noise gate reset hold time setting.
The noise gate is not reset for the hold time set in Register 0xC6.
Hold time reset after noise gate
Hold time no reset after noise gate
ALC Embedded High-Pass Filter Enable. ALC high-pass filter enable/disable
setting. The high-pass filter is fixed at 3.7 Hz at a 48 kHz sample rate.
High-pass filter enable
High-pass filter disable
ALC Noise Gate Mode. ALC noise gate mode selection: Noise Gate Mode 1,
Noise Gate Mode 2, Noise Gate Mode 3, or disable noise gate.
No noise gate
Noise Gate Mode 1; keeps the gain before ALC enters noise gate
Noise Gate Mode 2; sets the PGA gain to 0 dB
Noise Gate Mode 3; mutes the ALC output to −120 dB
ALC Enable Control. ALC enable/disable control.
Both channels disabled
Right channel enabled
Left channel enabled
Both channels enabled
ALC Operation Mode Control. ALC can be applied to digital/analog PGA or
both by setting this register.
Control digital PGA
Control analog PGA
Control both analog/digital PGA
No use
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Reset
0x0
0x0
0x0
0x0
0x0
ADAU1373
Access
RW
RW
RW
RW
RW