adau1373 Analog Devices, Inc., adau1373 Datasheet - Page 52

• Manufacturer Part Number: adau1373
• Description: Low Power Codec With Speaker And Headphone Amplifier Adau1373
• Manufacturer: Analog Devices, Inc.

ADAU1373
Bits
3
2
1
0
DIGITAL MICROPHONE INPUT INTERFACE
The ADAU1373 supports the digital microphone inputs.
The digital microphone output data can be connected at the
DMIC1_2_DATA and DMIC3_4_DATA pins (Ball B4 and Ball C6,
respectively). The bit clock for the digital microphone is avail-
able at the DMIC_CLK pin (Ball A4). The bit clock is fixed at
64 × f
Four digital microphones or two stereo pairs of digital micro-
phones can be connected to the ADAU1373 (see Figure 95
and Figure 96). The single pair of digital microphones shares
the decimator with ADC; therefore, when using DMIC1_2_DATA,
the ADC is not available. However, DMIC3_4_DATA has a
separate decimator and, therefore, can be used independently.
Figure 95. Digital Microphone Connection Diagram for Four Microphones
S
ADAU1373
DMIC1_2_DATA
DMIC3_4_DATA
(see Figure 5 for the waveforms).
Bit Name
DPLLx_LOCKED
PLLx_LOCKED
DPLLx_BYPASS
PLLx_EN
DMIC_CLK
IOVDD4
Settings
DMIC1
DMIC2
DMIC3
DMIC4
Description
DPLLx lock (read-only bit). This bit is stored in Register 0x2E for PLLA (Bit 3) and Register
0x35 for PLLB (Bit 3).
0: DPLLx unlocked (default).
1: DPLLx locked.
APLL lock (read-only bit). This bit is stored in Register 0x2E for PLLA (Bit 2) and Register
0x35 for PLLB (Bit 2).
0: APLL unlocked (default).
1: APLL locked.
DPLL bypass bit. This bit is stored in Register 0x2E for PLLA (Bit 1) and Register 0x35 for
PLLB (Bit 1).
0: DPLLx not bypassed (default).
1: DPLLx bypassed.
APLL enable bit. This bit is stored in Register 0x2E for PLLA (Bit 0) and Register 0x35 for
PLLB (Bit 0).
0: APLL disabled (default).
1: APLL enabled.
0.1µF
Rev. 0 | Page 52 of 296
Figure 96. Digital Microphone Connection Diagram for Two Microphones
To enable digital microphone support, the digital recording engine
must be enabled first, using Register 0xEB. The Digital Micro-
phone 1/Digital Microphone 2 engine can be enabled using Bit 2
of Register 0xEB, and the Digital Microphone Input 3/Digital
Microphone 4 engine can be enabled using Bit 3 of Register 0xEB.
After the recording engine is enabled, the digital microphone
input block can be enabled using Register 0xE2, Bit 0 for Input 1/
Input 2 (DMIC1_2_DATA) and Bit 2 for Input 3/Input 4
(DMIC3_4_DATA). The digital microphone data input is then
routed through the decimator and the recording engine to
digital mix/mux.
By default, the digital microphone inputs are configured as a stereo
pair. If using only one microphone, use Register 0xE2, Bit 7, to
set it as mono input.
The bit clock required for the digital microphone is available at
the DMIC_CLK pin (Ball A4), and the drive capability can be
set using Register 0xE9, Bit 3.
ADAU1373
DMIC1_2_DATA
DMIC3_4_DATA
DMIC_CLK
IOVDD4
DMIC1
DMIC2
0.1µF