adau1373 Analog Devices, Inc., adau1373 Datasheet - Page 59

• Manufacturer Part Number: adau1373
• Description: Low Power Codec With Speaker And Headphone Amplifier Adau1373
• Manufacturer: Analog Devices, Inc.

The DRCs consist of both peak and rms signal detectors.
Either the peak or the rms detector can be assigned for noise gate,
compressor/expander, and limiter. Bits[5:3] in Register 0x8D,
Register 0x9D, and Register 0xAD are provided for selecting the
detectors, as follows:
•
•
•
The DRC can be set to function as limiter, compressor,
expander, or noise gate. See Figure 107 for the input/output plot
showing the various modes of operation of the DRC.
The DRC allows flexibility in setting up the thresholds, as well
as attack and release time controls. The DRC allows independent
adjustment of the thresholds by providing control of the x-axis
and y-axis using Register 0x82 to Register 0x89 for DRC1,
Register 0x92 to Register 0x99 for DRC2, and Register 0xA2
to Register 0xA9 for DRC3. Bit DRCTHX1 to Bit DRCTHX4 in
these registers can be used to set the input level threshold point
on the x-axis, and Bit DRCTHY1 to Bit DRCTHY4 can be used
to set the output level point on the y-axis. The available range is
−96 dB to 0 dB for each threshold.
Table 19. DRC Setting Bits and Functions
Register Address
0x8C, 0x9C, 0xAC
0x8D, 0x9D, 0xAD
0x8D, 0x9D, 0xAD
0x8D, 0x9D, 0xAD
0x8D, 0x9D, 0xAD
0x8D, 0x9D, 0xAD
0x8D, 0x9D, 0xAD
0x8D, 0x9D, 0xAD
Table 20. DRC Dynamic Behavior Control
Register Address
0x80, 0x90, 0xA0
0x81, 0x91, 0xA1
0x81, 0x91, 0xA1
0x8A, 0x9A, 0xAA
0x8A, 0x9A, 0xAA
0x8B, 0x9B, 0xAB
0x8B, 0x9B, 0xAB
The DRCNGSRC bit (Bit 5) can be used for selecting the
noise gate detector.
The DRCCESRC bit (Bit 4) can be used for selecting the
compressor/expander detector.
The DRCLMSRC bit (Bit 3) can be used for selecting the
limiter detector.
Bits
[5:2]
7
6
5
4
3
2
[1:0]
Bits
[3:0]
[7:4]
[3:0]
[7:4]
[3:0]
[7:4]
[3:0]
Bit Name
DRCG
DRCNGTGT
DRCNGHDEN
DRCNGSRC
DRCCESRC
DRCLMSRC
DRCNGEN
DRCEN
Bit Name
DRCLELTAV
DRCLELATT
DRCLELDEC
DRCGSATT
DRCGSDEC
DRCHTNOR
DRCHTNG
Description
Sets the DRC gain; available range is from −24 dB to +21 dB.
Sets the DRC noise gate target.
Enables or disables the DRC noise gate recovery hold.
Selects the DRC noise gate level detector; selects either rms or peak detector.
Selects the DRC compressor/expander level detector; selects either rms or peak detector.
Selects the DRC limiter level detector; selects either rms or peak detector.
Noise gate enable control; provides independent noise gate control.
DRC enable control; enables or disables the DRC. The input source for the DRC can be
selected as left channel, right channel, or both.
Description
Sets rms signal detector averaging time. Available range is from 750 μs to 24.576 sec.
Sets DRC attack time. Available range is 46.875 μs to 1.536 sec.
Sets DRC decay (release) time. Available range is 0.75 ms to 24.576 sec.
Sets DRC gain smooth attack time. Available range is 46.875 μs to 1.536 sec.
Sets DRC gain smooth decay time. Available range is 0.75 ms to 24.576 sec.
Sets DRC normal operation hold time. Available range is from 0 ms up to 1.37 sec; value
increments by 2× the previous value, beginning with 0.67 ms.
Sets DRC noise gate hold time. Available range is from 0 ms up to 1.37 sec; value increments by
2× the previous value, beginning with 0.67 ms.
Rev. 0 | Page 59 of 296
The DRC gain can be set using the DRCG bits (Bits[5:2]) in
Register 0x8C, Register 0x9C, and Register 0xAC. The range
available is −24 dB to +21 dB. See Table 19 for a listing of the
DRC detector selection registers and bits and their functions.
Table 20 lists the registers and bits that control the dynamic
behavior of the DRC.
DRCTHY1
DRCTHY2
DRCTHY3
DRCTHY4
OUTPUT
Figure 107. DRC Output vs. Input Plot
DRCTHX4 DRCTHX3
NOISE GATE
POINT4
POINT3
EXPANDER
DRCTHX2 DRCTHX1
POINT2
COMPRESSOR
ADAU1373
POINT1
LIMITER
INPUT