ucb1300 NXP Semiconductors, ucb1300 Datasheet - Page 29

• Manufacturer Part Number: ucb1300
• Description: Advanced Modem/audio Analog Front-end
• Manufacturer: NXP Semiconductors

Philips Semiconductors
SIB DATA FORMAT
The first 64 bits in the SIB-frame are read and written by the UCB1300. They contain audio and telecom codec data fields,
several control bits, and a control register data field, as defined in table below.
SIB DATA FORMATS
Since the data transfer is completely synchronous, a given control register may be written many times, before the device
feeding the data has a chance to change the control bits. The UCB1300 does detect whether the data is changed or not.
CONTROL REGISTER DATA TRANSFER
The last 16 bits of the UCB1300 word is made up of control register data. The selection of the control register and whether
it is read or written is defined by the control register address field [bit 17:20] and the “write” bit [bit 21]. For a read action
of a control register, the control register address field has to be set to the desired control register address and the “write”
bit has to be set to zero in the SIBDIN stream. The read data is sent by the UCB1300 within the control register data field
of SIBDOUT during the same frame as the read request occurred. In addition, during a read cycle, the control register
data field of SIBDIN is ignored by the UCB1300, which implies that no modifications of the UCB1300 settings can be
performed when the “write” bit equals zero in the SIBDIN data-stream.
For a write cycle (“write” bit = 1), the control register data contents of SIBDIN are written to the UCB1300 register selected
by the register address field after reception of the complete first word (the update is performed during the 64th bit in the
SIB frame). This implies that the control register data contents of SIBDOUT data-stream in a SIB frame represents the
previous contents of the selected control register.
The control register address in the SIBDOUT data-stream is a copy of the selected control register in the SIB
data-stream. These bits show an additional delay, since they pass through additional circuitry.
The control register data is actually written in the control registers after the transfer of the first SIB word is completed.
This implies that the control register data is updated during bit 64 of the SIB frame. The control data is only updated when
the write bit is '1' in the SIB frame. The control data will not be updated when the write bit equals '0'. This simplifies the
read out of control register data, since it is not required to send 'valid' data in the control register data field when a control
register is read if the write bit is kept at '0'.
2000 Jun 26
0 - 11
12 - 16
17 - 20
21
22 - 29
30
31
32 - 45
46 - 47
48 - 63
SIB FRAME
Advanced modem/audio analog front-end
BIT
audio input path data (12 bits); bit 0 = MSB
not read but reserved
control register address (4 bits); bit 17 = MSB
write bit (write 1)
not read but reserved
audio valid sample flag
telecom valid sample flag
telecom input path data (14 bits)
not read but reserved
control register write data (16 bit); bit 48 = MSB control register read data (16 bit); bit 48 = MSB
SIBDIN FIELD DEFINITION
29
audio output path data (12 bits); bit 0 = MSB
fixed ‘0’
control register address (4 bits); bit 17 = MSB; is a
copy of the register address as present in the
SIBDIN field in the same SIB frame.
fixed ‘0’
fixed ‘0’
audio valid flag
telecom valid flag
telecom output path data (14 bits); bit 32 = MSB
fixed ‘0’
SIBDOUT FIELD DEFINITION
Product specification
UCB1300