ucb1100 NXP Semiconductors, ucb1100 Datasheet - Page 19

• Manufacturer Part Number: ucb1100
• Description: Advanced Modem/audio Analog Front-end
• Manufacturer: NXP Semiconductors

Philips Semiconductors
6.5 10 bit ADC
The UCB1100 includes a 10 bit successive approximation analogue
to digital converter (ADC) with build in track and hold circuitry, an
analogue multiplexer to select 4 analogue inputs or the 5 touch
screen voltages and 4 switched resistive voltage dividers on the
analogue ad0–3 high voltage inputs. The ADC is used to readout the
touch screen inputs and it measures the voltage on the four
analogue high voltage inputs ad0–3.
The ADC is controlled through the SIB interface. It is enabled by the
adc_enable bit in register 10; the ADC circuitry, including the track
and hold circuitry does not consume any power when it is not
enabled.
A complete analogue to digital conversion consists of several
phases. First the ADC input selector must be set to the proper input.
Secondly the track and hold must track the signal; this requires a
certain settling time if the adc input was changed. After this time the
sample is taken. A calibration of the ADC circuitry is performed
before the actual conversion starts. The result of the conversion is
stored in the register 11 of the SIB interface, after the completion of
1998 May 08
Advanced modem/audio analog front-end
adc_input_selection
adc_dat_valid
’adc state’
adc_start
adc_data
adc_ena
Figure 20. Timing Diagram of an ADC Conversion Sequence (adc_sync_ena=‘0’)
9 to 1
track
mux
internal reference
tadcena
Figure 19. Block Diagram of the 10 bit ADC Circuit
tadctrk
track & hold
cal
tadccal
10 bit ADC
19
conversion
to external register 11
tconv
the conversion. An interrupt may be generated whenever a
conversion is completed, depending of the setting of the
adc_interrupt_ena bits in the sib register 2 and 3. The
adc_data_valid bit in the SIB register 11 indicates the status of the
ADC; it equals ‘0’ when a ADC sequence is started and it equals ‘1’
when the ADC result is stored in the SIB register 11.
The ADC sequence is started in two ways. First it starts whenever
the adc_start bit in register 10 is changed from ‘0’ to ‘1’; this is the
case when the adc_sync_ena bit in registers 10 equals ‘0’
(=default). Internal logic determines whether the adc input
multiplexer setting was changed in the sib frame, carrying the
adc_start bit transition. If this is the case, an additional tracking time
is added automatically.
The second mode of operation is activated when the adc_sync_ena
bit is set to ‘1’. In this mode the ADC conversion is not started by an
‘0’ to ‘1’ transition of the adc_start bis, but is ‘armed’. During the
arming situation the track and hold circuit tracks the selected input
signal. A sample is taken and the actual ADC conversion is started
when a rising edge is detected on the adcsync input pin.
10
ADC start
stop logic
adc_sync_ena
SN00144
adc
start
sync
enable
adcsync
track
Preliminary specification
SN00145
UCB1100