sc18is600 NXP Semiconductors, sc18is600 Datasheet
sc18is600
Available stocks
Related parts for sc18is600
sc18is600 Summary of contents
Page 1
... SC18IS600/601 SPI to I Rev. 03 — 13 December 2006 1. General description The SC18IS600/601 is designed to serve as an interface between the standard SPI of a host (microcontroller, microprocessor, chip set, etc.) and the serial I the host to communicate directly with other I operate controls all the I The key distinction between the SC18IS600 and the SC18IS601 lies in the clock source: internal (SC18IS600) versus external (SC18IS601) ...
Page 2
... SC18IS600 CONTROL RESET LOGIC MISO MOSI SPI SCLK CS INT INTERRUPT CONTROL LOGIC OSCILLATOR ON-CHIP RC OSCILLATOR Fig 1. Block diagram of SC18IS600 SC18IS600_601_3 Product data sheet BUFFER CONTROLLER GENERAL PURPOSE Rev. 03 — 13 December 2006 SC18IS600/601 2 SPI to I C-bus interface SDA 2 I C-BUS SCL GPIO0 ...
Page 3
... INT INTERRUPT CONTROL external clock input OSCILLATOR (CLKIN) Fig 2. Block diagram of SC18IS601 SC18IS600_601_3 Product data sheet LOGIC SPI LOGIC Rev. 03 — 13 December 2006 SC18IS600/601 SPI C-BUS BUFFER CONTROLLER GENERAL PURPOSE I/Os 002aab784 © NXP B.V. 2006. All rights reserved. 2 C-bus interface ...
Page 4
... INT is reset (deactivated) either when the I2CStat register is read result of a master reset (RESET). This pin is an open-drain pin. I/O Wake up the SC18IS600/601 from the Power-down mode. Pulled LOW by the host to wake-up from low power state. This pin can also be used as a quasi-bidirectional I/O when not in a power-down state. ...
Page 5
... NXP Semiconductors 6. Functional description The SC18IS600/601 acts as a bridge between a SPI interface and an I SPI master device to communicate with I Mode 3 of the SPI specification and can operate Mbit/s (SC18IS601). 6.1 Internal registers The SC18IS600/601 provides internal registers for monitoring and control. These registers are shown in paragraphs ...
Page 6
... HIGH. The quasi-bidirectional pin configuration is shown in Although the SC18IS600/601 device, most of the pins are 5 V tolerant applied to a pin configured in quasi-bidirectional mode, there will be a current flowing from the pin to V confi ...
Page 7
... SC18IS600_601_3 Product data sheet Figure pin latch data V SS input data Figure input data glitch rejection Figure Rev. 03 — 13 December 2006 SC18IS600/601 2 SPI to I C-bus interface 6. GPIO pin glitch rejection 002aab883 Schmitt-triggered input that GPIO pin 002aab884 8. © NXP B.V. 2006. All rights reserved. ...
Page 8
... A read from this register returns states of all pins. GPIO1 GPIO0 2 C-bus device address used by the bus master. 2 C-bus clock frequency. Various clock rates are shown in for the SC18IS600. The frequency can be determined using the following formula: 7.3728 10 = ------------------------------ - 2CClk Rev. 03 — 13 December 2006 ...
Page 9
... The least significant bit of I2CTO (TE bit) is used as a time-out enable/disable. A logic 1 will enable the time-out function. On the SC18IS600 the time-out oscillator operates at 57.6 kHz. For the SC18IS601 the time-out oscillator frequency can be determined using the following formula: Time-out oscillator frequency This oscillator is fed into a 16-bit down counter. The down counter’s lower nine bits are loaded with ‘ ...
Page 10
... An interrupt is generated on INT C-bus device address not acknowledged C-bus slave has not acknowledged the byte that has just been transmitted by the SC18IS600/601. An interrupt is generated on INT C-bus busy. The SC18IS600/601 is busy 2 performing an I C-bus transaction, no new transaction should be initiated by the host. No interrupt is generated ...
Page 11
... SCLK, MOSI and MISO are typically tied together between two or more SPI devices. Data flows from the master to the SC18IS600/601 on the MOSI (Master Out Slave In) pin and flows from SC18IS600/601 to the master on the MISO (Master In Slave Out) pin. The SCLK signal is an input to the SC18IS600/601. ...
Page 12
... INT pin, and the ‘transaction completed’ status can be read in I2CStat. Note that the third byte sent by the host is the device I SC18IS600/601 will ignore the least significant bit so a write will always be performed even if the least significant bit is a ‘1’. ...
Page 13
... Note that the third byte sent by the host is the device slave address. The SC18IS600/601 will ignore the least significant bit so a read will always be performed even if the least significant bit is a ‘0’. The maximum number of bytes to be read is 96. ...
Page 14
... NXP Semiconductors When the host issues a Read Buffer command, the SC18IS600/601 will return the data in the read buffer on the MISO pin. Note that the Read Buffer will be overwritten if an additional ‘Read N bytes’ ‘Read after write’ command is executed before the Read Buffer command ...
Page 15
... A Read Register function is initiated by sending a 0x21 command followed by an internal register address to be read (see read register is returned by the SC18IS600 on the MISO pin. Only one register can be accessed in a single transaction. There is no auto-incrementing of the register address. Note that write and read from internal registers are processed immediately as soon as the SC18IS600/601 determines the intended register ...
Page 16
... NXP Semiconductors 6.6.9 Power-down mode Fig 20. Power-down mode The SC18IS600/601 can be placed in a low-power mode where the internal oscillator is stopped and it will no longer respond to SPI messages. Enter the Power-down mode by sending the power-down command (0x30) followed by the two defined bytes, which are 0x5A followed by 0xA5 ...
Page 17
... OH push-pull mode all pins quasi-bidirectional mode [2] [3] logical 0 [4] all ports [5][6] all ports; logical 1-to Rev. 03 — 13 December 2006 SC18IS600/601 2 SPI to I C-bus interface [1] Min Typ Max - 3.6 4 < 0 0.22V ...
Page 18
... Dynamic characteristics Table 12. Dynamic characteristics +85 C (industrial); unless otherwise specified. DD amb Symbol Parameter f internal RC oscillator osc(RC) frequency (SC18IS600) External clock input (SC18IS601); see f oscillator frequency osc T clock cycle time CLCL t clock HIGH time CHCX t clock LOW time ...
Page 19
... NXP Semiconductors Table 13. Dynamic characteristics +85 C (industrial); unless otherwise specified. DD amb Symbol Parameter f internal RC oscillator osc(RC) frequency (SC18IS600) External clock input (SC18IS601); see f oscillator frequency osc T clock cycle time CLCL t clock HIGH time CHCX t clock LOW time ...
Page 20
... SPIOH SPIOH t t SPIDV SPIDV t SPIA slave MSB/LSB out t t SPIDSU SPIDH MSB/LSB in 0.2V 0 0.2V 0 CHCL CLCX Rev. 03 — 13 December 2006 SC18IS600/601 SPI SPIR t SPILAG t SPIOH t SPIDV t SPIDIS slave LSB/MSB out SPIDSU SPIDSU SPIDH LSB/MSB in 002aab797 t CHCX t CLCH ...
Page 21
... SPICLKW t 002aab929 t SPILAG1 ( s) 12.00 18.00 CLKIN frequency (MHz) Fig 25. t 160 120 1.843 3.687 7.373 12.00 CLKIN frequency (MHz) Rev. 03 — 13 December 2006 SC18IS600/601 SPI to I Min Typ 8 - refer to Figure 24 refer to Figure 25 2 C-bus refer to Figure 26 t SPILAG1 CSW ...
Page 22
... SC18IS600_601_3 Product data sheet 2.5 scale (1) ( 0.30 0.2 5.1 4.5 0.65 0.19 0.1 4.9 4.3 REFERENCES JEDEC JEITA MO-153 Rev. 03 — 13 December 2006 SC18IS600/601 SPI detail 6.6 0.75 0.4 1 0.2 0.13 6.2 0.50 0.3 EUROPEAN PROJECTION ...
Page 23
... Solder bath specifications, including temperature and impurities SC18IS600_601_3 Product data sheet Rev. 03 — 13 December 2006 SC18IS600/601 2 SPI to I C-bus interface © NXP B.V. 2006. All rights reserved ...
Page 24
... Lead-free process (from J-STD-020C) Package reflow temperature ( C) 3 Volume (mm ) < 350 260 260 250 Figure 28. Rev. 03 — 13 December 2006 SC18IS600/601 2 SPI to I C-bus interface Figure 28) than a PbSn process, thus 350 220 220 350 to 2000 > 2000 260 260 250 245 ...
Page 25
... American Standard Code for Information Interchange General Purpose Input/Output Universal Asynchronous Receiver/Transmitter Least Significant Bit Most Significant Bit Inter IC bus Serial Peripheral Interface Rev. 03 — 13 December 2006 SC18IS600/601 2 SPI to I C-bus interface peak temperature time 001aac844 © NXP B.V. 2006. All rights reserved. ...
Page 26
... SCL: changed Type from “I/O” to “O”; changed Description 2 C-bus serial clock input/output” to “I 2 C-bus status”: added column “Register value” Figure 19 “Read from SC18IS600/601 internal register” to “dummy byte” on signal MOSI st st paragraph, 1 sentence: appended “and a dummy byte” to end of sentence characteristics” ...
Page 27
... Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners C-bus — logo is a trademark of NXP B.V. http://www.nxp.com salesaddresses@nxp.com Rev. 03 — 13 December 2006 SC18IS600/601 2 SPI to I C-bus interface © NXP B.V. 2006. All rights reserved ...
Page 28
... C-bus slave device . . . . 13 2 6.6.3 I C-bus read after write 6.6.4 Read buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2 6.6.5 I C-bus write after write . . . . . . . . . . . . . . . . . 14 6.6.6 SPI configuration . . . . . . . . . . . . . . . . . . . . . . 14 6.6.7 Write to SC18IS600/601 internal registers . . . 15 6.6.8 Read from SC18IS600/601 internal register 6.6.9 Power-down mode . . . . . . . . . . . . . . . . . . . . . 16 7 Limiting values Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . 18 10 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 22 11 Soldering ...