isp1561 NXP Semiconductors, isp1561 Datasheet
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isp1561 Summary of contents
Page 1
... Windows standard OHCI and EHCI drivers that are present in Windows 98 Second Edition (SE), Windows Millennium Edition (Me), Windows XP and Windows 2000. The ISP1561 directly interfaces to any 32-bit, 33 MHz PCI bus. It has 5 V tolerant PCI pins that can source 3.3 V. The PCI interface fully complies with Specifi ...
Page 2
... Ref. 8 “Universal Serial Bus Specification” standby and wake-up modes; all I/O pins are cold Ref. 5 “PCI Bus Power Management Interface Specification” Rev. 02 — 5 March 2007 ISP1561 HS USB PCI Host Controller Ref. 4 “Open Host Controller Ref. 2 “Enhanced Host Controller Ref. 6 “PCI Local Bus ...
Page 3
... Type number Package Name ISP1561BM LQFP128 ISP1561_2 Product data sheet Description plastic low profile quad flat package; 128 leads; body 14 Rev. 02 — 5 March 2007 ISP1561 HS USB PCI Host Controller Version 14 1.4 mm SOT420-1 © NXP B.V. 2007. All rights reserved 103 ...
Page 4
... OC2 OC3 AMB2 AMB3 GRN2 GRN3 GL2 GL3 PWE2 PWE3 DM2 DP1 DP2 7 ISP1561BM IRQ1 8 IRQ12 12 KBIRQ1 13 MUIRQ12 11 A20OUT 6, 14, 21, 29, 37, 45, 53, DGND 61, 69, 76, 83, 86, 128 SEL2 9 PORTS EHCI (FUNCTION 2) ...
Page 5
... TTL with hysteresis tolerant 10 - supply voltage (3.3 V) Rev. 02 — 5 March 2007 ISP1561 HS USB PCI Host Controller 96 65 004aaa931 [2] [2] © NXP B.V. 2007. All rights reserved. ...
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... I/O bit 22 of multiplexed PCI address and data 39 I/O bit 21 of multiplexed PCI address and data 40 I/O bit 20 of multiplexed PCI address and data Rev. 02 — 5 March 2007 ISP1561 HS USB PCI Host Controller [3] [3] © NXP B.V. 2007. All rights reserved 103 ...
Page 7
... I/O bit 9 of multiplexed PCI address and data 71 I/O bit 8 of multiplexed PCI address and data 72 I/O byte 0 of multiplexed PCI bus command and byte enable Rev. 02 — 5 March 2007 ISP1561 HS USB PCI Host Controller © NXP B.V. 2007. All rights reserved 103 ...
Page 8
... USB downstream port 2 (digital) push-pull; TTL with hysteresis tolerant 97 O power enable for USB downstream port 2 (open-drain slew rate control; TTL tolerant Rev. 02 — 5 March 2007 ISP1561 HS USB PCI Host Controller © NXP B.V. 2007. All rights reserved 103 ...
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... D+; analog connection for USB downstream port 3 118 - analog ground 119 I overcurrent sense input for USB downstream port 4 (digital) push-pull; TTL with hysteresis tolerant Rev. 02 — 5 March 2007 ISP1561 HS USB PCI Host Controller 1 %) © NXP B.V. 2007. All rights reserved 103 ...
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... LED is off by default; the LED can be programmed to enable it to blink 10 ns slew rate control; TTL tolerant 128 - digital ground Rev. 02 — 5 March 2007 ISP1561 HS USB PCI Host Controller cold cold 2 C EEPROM is not used. © NXP B.V. 2007. All rights reserved. ...
Page 11
... Indication of a good USB connection is provided through the GoodLink technology (open-drain, a maximum current of 20 mA). During enumeration, LED indicators blink on momentarily corresponding to the enumeration traffic of ISP1561 downstream ports. The LED also blinks on whenever there is valid traffic to the downstream port. In suspend mode, the LED is off. The GoodLink feature provides a user-friendly indication on the status of the USB traffi ...
Page 12
... PCI configuration space Ref. 6 “PCI Local Bus Specification” ISP1561 provides its own PCI configuration registers, which can vary in size. In addition to the basic PCI configuration header registers, these functions implement the capability registers to support power management. ...
Page 13
... PCI initiator and target A PCI initiator initiates PCI transactions to the PCI bus. A PCI target responds to PCI transactions as a slave. In the ISP1561, the two open Host Controllers and the enhanced Host Controller function as both initiators or targets of PCI transactions issued by the host CPU. ...
Page 14
... Value Description [1] X Device ID: This register value is defined by NXP Semiconductors to identify the USB Host Controller IC product. For the ISP1561, NXP Semiconductors has defined OHCI functions as 1561h, and the EHCI function as 1562h. Rev. 02 — 5 March 2007 HS USB PCI Host Controller …continued ...
Page 15
... PERR# and continues normal operation. The state of this bit after RST# is logic 0. Devices that check parity must implement this bit. Devices are required to generate parity, even if parity checking is disabled. Rev. 02 — 5 March 2007 ISP1561 HS USB PCI Host Controller ...
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... 66MC Rev. 02 — 5 March 2007 HS USB PCI Host Controller …continued Table 8 STA DEVSELT[1: reserved ISP1561 9 8 MDPE © NXP B.V. 2007. All rights reserved 103 ...
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... A value of logic 0 indicates that no new capabilities linked list is available. A value of logic 1 indicates that the value read at offset 34h is a pointer in configuration space to a linked list of new capabilities. - reserved Rev. 02 — 5 March 2007 ISP1561 HS USB PCI Host Controller © NXP B.V. 2007. All rights reserved 103 ...
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... EHCI, which is USB 2.0 specification compliant. Rev. 02 — 5 March 2007 HS USB PCI Host Controller Table 10 0Ch 03h [ ISP1561 Table © NXP B.V. 2007. All rights reserved 103 ...
Page 19
... If the bit is logic 1, then the device has multiple functions. HT[6:0] Header Type: These bits identify the layout of the part of the predefined header, beginning at byte 10h in configuration space. Rev. 02 — 5 March 2007 ISP1561 HS USB PCI Host Controller Table 13 shows the bit 15). 3 ...
Page 20
... R/W Base Address register (BAR1 — (address: 14h, 18h, 1Ch, 20h and 24h): The BAR1 register spaces are not used in the ISP1561. 8.2.1.12 CardBus CIS Pointer register (address: 28h) This 4-byte register is used by devices that want to share silicon between CardBus and PCI ...
Page 21
... EPROMs for expansion ROM. This 4-byte register at offset 30h in a type 00h predefined header is defined to handle the base address and size information for this expansion ROM. The ISP1561 does not support expansion EPROM. 8.2.1.16 Capabilities Pointer register (address: 34h) The Capabilities Pointer register is used to point to a linked list of new capabilities implemented by the device ...
Page 22
... This register determines the delay to set the UE bit if a RETRY time-out occurs. ISP1561_2 Product data sheet Table 22. Value Description 01h Interrupt Pin: INTA# is the default interrupt pin used by the ISP1561. Table 23. Value Description [1] X MIN_GNT used to specify how long a burst period the device needs, assuming a clock rate of 33 MHz ...
Page 23
... SOF counter clock periods to generate a SOF micro frame length, is equal to 59488 + value in this field. The default value is decimal 32 (20h), which gives a SOF cycle time of 60000. See FLADJ value as a function of SOF cycle time Rev. 02 — 5 March 2007 ISP1561 HS USB PCI Host Controller Table 25. 3 ...
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... Power Management Control/Status PCI-to-PCI Bridge Support Extensions (PMCSR_BSE) Data Value Description 01h ID: This field when 01h identifies the linked list item as being PCI power management registers. Rev. 02 — 5 March 2007 ISP1561 HS USB PCI Host Controller …continued SOF cycle time (480 MHz) : 59984 60000 : 60480 ...
Page 25
... D1_S D1 Support: If this bit is logic 1, this function supports the D1 power management state. Functions that do not support D1 must always return a value of logic 0 for this bit. Rev. 02 — 5 March 2007 ISP1561 HS USB PCI Host Controller Table 33) describes the location 11 10 ...
Page 26
... The logic level of the AMB4 pin at power-on determines the default value of PMC registers. If this pin is connected to V the case of notebook design). If this pin is left open or is pulled down, then the ISP1561 does not support D3 8.2.3.4 PMCSR register (address: value read from address 34h + 4h) ...
Page 27
... Functions that do not support the PME# generation from any D-state (that is, PMC[15:11 0000b), may hardwire this bit to be read-only always returning logic 0 when read by system software. - reserved Rev. 02 — 5 March 2007 ISP1561 HS USB PCI Host Controller D_S[3:0] 0 ...
Page 28
... This bit is only meaningful if bit 7 (BPCC_EN) is logic 1. - reserved Rev. 02 — 5 March 2007 HS USB PCI Host Controller …continued reserved The state of this bit determines the action that hot © NXP B.V. 2007. All rights reserved. ISP1561 Table 40 . hot , its hot , its hot 28 of 103 ...
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... Rev. 02 — 5 March 2007 HS USB PCI Host Controller Resultant actions by bridge (either direct or indirect) none none clock stopped on secondary bus clock stopped and V removed from secondary bus CC (B3 only); for definition of B2_B3#, see none ISP1561 Table 39 © NXP B.V. 2007. All rights reserved 103 ...
Page 30
... The ISP1561 can be connected to an external EEPROM through the I The hardware connections are shown in Fig 3. EEPROM connection diagram The slave address that the ISP1561 uses to access the EEPROM is 101 0000b. Page mode addressing is not supported. Therefore, pins A0, A1 and A2 of the EEPROM must be connected to ground (logic 0). ...
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... Device ID (DID), Vendor ID (VID), subsystem VID and subsystem DID assigned to NXP Semiconductors by PCI-SIG will be loaded. See value. For instructions on programming the EEPROM, refer to application note “Designing a Hi-Speed USB Host PCI Adapter Using the ISP1561” 3 “ISP1561 Evaluation Board User’s address Fig 4 ...
Page 32
... BAR0. The HCD can access these registers by using the address of base address value + offset. contains a list of Host Controller registers. ISP1561_2 Product data sheet Rev. 02 — 5 March 2007 ISP1561 HS USB PCI Host Controller Table 42 © NXP B.V. 2007. All rights reserved 103 ...
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Table 42. USB Host Controller registers Address OHCI register (Hex) Func0 OHCI1 (2 ports) 00 HcRevision 0000 0110 04 HcControl 0000 0000 08 HcCommandStatus 0000 0000 0C HcInterruptStatus 0000 0000 10 HcInterruptEnable 0000 0000 14 HcInterruptDisable 0000 0000 18 HcHCCA ...
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... HceStatus 0000 0000 [1] Reset values that are highlighted (for example, 0) are the ISP1561 implementation specific reset values, and reset values that are not highlighted (for example, 0) are compliant with OHCI and EHCI specification. [1] Reset hex value Func0 OHCI1 ...
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... REV[7: Rev. 02 — 5 March 2007 ISP1561 HS USB PCI Host Controller © NXP B.V. 2007. All rights reserved. ...
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... BLE CLE R/W R/W Rev. 02 — 5 March 2007 ISP1561 HS USB PCI Host Controller RWE RWC R/W R PLE CBSR[1: R/W R/W R/W © ...
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... When disabled, the HCD may modify the list. If HcBulkCurrentED is pointing to an Endpoint Descriptor (ED removed, the HCD must advance the pointer by updating HcBulkCurrentED before re-enabling processing of the list. Rev. 02 — 5 March 2007 ISP1561 HS USB PCI Host Controller © NXP B.V. 2007. All rights reserved 103 ...
Page 38
... After a reset, the HCD is responsible for restoring this value. 00b — 01b — 10b — 11b — Table 47 shows the bit allocation of the HcCommandStatus Rev. 02 — 5 March 2007 ISP1561 HS USB PCI Host Controller …continued © NXP B.V. 2007. All rights reserved. USB”). If set 38 of 103 ...
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... found on the bulk list, and if the HCD does not set BLF, then BLF is still logic 0 when the Host Controller completes processing the bulk list and the bulk list processing stops. Rev. 02 — 5 March 2007 ISP1561 HS USB PCI Host Controller 27 26 ...
Page 40
... MIE (Master Interrupt Enable) bit is set. The HCD may clear reserved reserved Rev. 02 — 5 March 2007 ISP1561 HS USB PCI Host Controller …continued Table 49. When an event occurs, the reserved ...
Page 41
... HccaDoneHead. SO Scheduling Overrun: This bit is set when USB schedules for current frame overruns and after the update of HccaFrameNumber. A scheduling overrun causes the SOC (Scheduling Overrun Count) of HcCommandStatus to be incremented. Rev. 02 — 5 March 2007 ISP1561 HS USB PCI Host Controller WDH ...
Page 42
... Enables interrupt generation because of root hub status change FNO Frame Number Overflow: 0 — Ignore 1 — Enables interrupt generation because of frame number overflow UE Unrecoverable Error: 0 — Ignore 1 — Enables interrupt generation because of unrecoverable error Rev. 02 — 5 March 2007 ISP1561 HS USB PCI Host Controller reserved ...
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... FNO R/W R/W Rev. 02 — 5 March 2007 HS USB PCI Host Controller …continued Table 53 reserved WDH R/W R/W R/W ISP1561 R/W © NXP B.V. 2007. All rights reserved 103 ...
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... Ignore 1 — Disables interrupt generation because of HcDoneHead write-back SO Scheduling Overrun: 0 — Ignore 1 — Disables interrupt generation because of scheduling overrun Rev. 02 — 5 March 2007 ISP1561 HS USB PCI Host Controller Table 55. The HCD determines alignment © NXP B.V. 2007. All rights reserved 103 ...
Page 45
... Table 57 gives the bit allocation of the register PCED[27:20 PCED[19:12 PCED[11: Rev. 02 — 5 March 2007 ISP1561 HS USB PCI Host Controller R/W R/W R R/W R/W R R/W R/W R ...
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... HS USB PCI Host Controller 3 2 reserved 59 reserved ISP1561 © NXP B.V. 2007. All rights reserved 103 ...
Page 47
... Table 61 reserved Table 63. The register contains R/W R/W R/W ISP1561 R/W © NXP B.V. 2007. All rights reserved 103 ...
Page 48
... Host Controller. - reserved BCED[27:20 R/W R BCED[19:12 R/W R BCED[11: R/W R BCED[3: R/W R/W Rev. 02 — 5 March 2007 ISP1561 HS USB PCI Host Controller R/W R/W R R/W R/W R reserved Table 65 R/W R/W ...
Page 49
... HcDoneHead to the NextTD field of the TD. The Host Controller then overwrites the content of HcDoneHead with the address of this TD. This is set to logic 0 whenever the Host Controller writes the content of this register to HCCA. - reserved Rev. 02 — 5 March 2007 ISP1561 HS USB PCI Host Controller Table 67 contains the bit allocation ...
Page 50
... The HCD can then restore the stored value on completing the reset sequence. Rev. 02 — 5 March 2007 HS USB PCI Host Controller 27 26 FSMPS[14: R/W R/W R R/W R/W R FI[13: R/W R/W R R/W R/W R/W ISP1561 Table R/W © NXP B.V. 2007. All rights reserved 103 ...
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... Rev. 02 — 5 March 2007 HS USB PCI Host Controller reserved FR[13: R/W R/W R R/W R/W R/W Table 73. It provides © NXP B.V. 2007. All rights reserved. ISP1561 R R 103 ...
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... ED in that frame. After writing to HCCA, the Host Controller sets the SF (Start-of-Frame) in HcInterruptStatus. Table 75 reserved reserved R/W R/W Rev. 02 — 5 March 2007 ISP1561 HS USB PCI Host Controller FN[13: R/W R/W R R/W R/W R ...
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... LST[7: R/W R/W Rev. 02 — 5 March 2007 HS USB PCI Host Controller R/W R/W R/W 77 LST[11: R/W R/W R R/W R/W R/W ISP1561 R/W © NXP B.V. 2007. All rights reserved 103 ...
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... R/W R reserved NOCP R NDP[7: Rev. 02 — 5 March 2007 ISP1561 HS USB PCI Host Controller this field. The value R/W R/W R OCPM DT NPS R ...
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... Number Downstream Ports: These bits specify the number of downstream ports supported by the root hub implementation-specific. The minimum number of ports is 1. The maximum number of ports supported by OHCI is 15. Rev. 02 — 5 March 2007 ISP1561 HS USB PCI Host Controller 2 ms. Table 81. These fields are written during © ...
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... Device Removable: Each bit is dedicated to a port of the root hub. When cleared, the attached device is removable. When set, the attached device is not removable. Bit 0 — reserved Bit 1 — Device attached to port #1 Bit 2 — Device attached to port #2 Rev. 02 — 5 March 2007 ISP1561 HS USB PCI Host Controller ...
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... Remote Wake-up Enable). Writing logic 0 has no effect. Rev. 02 — 5 March 2007 HS USB PCI Host Controller reserved CCIC R reserved OCI © NXP B.V. 2007. All rights reserved. ISP1561 LPSC 0 R LPS 103 ...
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... PRSC R reserved PRS R/W Rev. 02 — 5 March 2007 ISP1561 HS USB PCI Host Controller …continued OCIC PSSC PESC R/W R/W R LSDA R POCI PSS PES ...
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... Port is suspended On write Clear Port Power: The HCD can clear the PPS (Port Power Status) bit by writing logic 1 to this bit. Writing logic 0 has no effect. Rev. 02 — 5 March 2007 ISP1561 HS USB PCI Host Controller © NXP B.V. 2007. All rights reserved 103 ...
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... On write Clear Suspend Status: The HCD can write logic 1 to initiate a resume. Writing logic 0 has no effect. A resume is initiated only if PSS (Port Suspend Status) is set. Rev. 02 — 5 March 2007 ISP1561 HS USB PCI Host Controller …continued © NXP B.V. 2007. All rights reserved 103 ...
Page 61
... USB legacy support registers The ISP1561 supports legacy keyboard and mouse. Four operational registers are used to provide the legacy support. Each of these registers is located on a 32-bit boundary. The offset of these registers is relative to the base address of the Host Controller operational registers with HceControl located at offset 100h. ...
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... OUT to port 64h sets IN_FULL to logic 0 and CMD_DATA to logic 1 in HceStatus IRQEN C_P R/W R/W R ISP1561 A20S R/W © NXP B.V. 2007. All rights reserved 103 ...
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... I/O registers 60h and 64h, and enables interrupts on IRQ1 or IRQ12, or both. The Host Controller also generates an emulation interrupt at appropriate times to invoke the emulation software reserved Rev. 02 — 5 March 2007 ISP1561 HS USB PCI Host Controller Table © NXP B.V. 2007. All rights reserved. 91. The ...
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... IN_DATA[7:0] Input Data: This register holds data that is written to I/O ports 60h or 64h reserved reserved reserved OUT_DATA[7: R/W R/W Rev. 02 — 5 March 2007 ISP1561 HS USB PCI Host Controller R/W R/W R/W Table 93 ...
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... I/O write to port 64h. Rev. 02 — 5 March 2007 HS USB PCI Host Controller Table CMD_DATA FLAG IN_FULL R/W R/W R/W ISP1561 contains the bit OUT_FULL 0 R/W © NXP B.V. 2007. All rights reserved 103 ...
Page 66
... HCIVERSION[15: HCIVERSION[7: CAPLENGTH[7: Rev. 02 — 5 March 2007 ISP1561 HS USB PCI Host Controller …continued Table 97 ...
Page 67
... Port Indicators: This bit indicates whether the ports support port INDICATOR indicator control. When this bit is logic 1, the port status and control registers include a read/writable field to control the state of the port indicator. Rev. 02 — 5 March 2007 ISP1561 HS USB PCI Host Controller Table 99 ...
Page 68
... Valid values are in the range Fh. Logic 0 in this field is undefined. Table reserved reserved Rev. 02 — 5 March 2007 HS USB PCI Host Controller …continued 101 ISP1561 © NXP B.V. 2007. All rights reserved 103 ...
Page 69
... Data structures using 32-bit address memory pointers 1 — Data structures using 64-bit address memory pointers shows the USBCMD register bit allocation reserved Rev. 02 — 5 March 2007 ISP1561 HS USB PCI Host Controller reserved ...
Page 70
... Logic 0 — Indicates the Light Host Controller Reset has completed and it is ready for the host software to re-initialize the Host Controller Logic 1 — Indicates the Light Host Controller Reset has not yet completed Rev. 02 — 5 March 2007 ISP1561 HS USB PCI Host Controller 19 18 ...
Page 71
... USBSTS register indicates when the Host Controller has finished the transaction and has entered the stopped state. Software must check HCH (HC Halted) in the USBSTS register is logic 1, before setting this bit. Rev. 02 — 5 March 2007 ISP1561 HS USB PCI Host Controller …continued © NXP B.V. 2007. All rights reserved. ...
Page 72
... When this bit and the PSE bit have the same value, the periodic schedule is either enabled (1) or disabled (0). RECL Reclamation Default. This is a read-only status bit that is used to detect an empty asynchronous schedule. Rev. 02 — 5 March 2007 ISP1561 HS USB PCI Host Controller ...
Page 73
... IOC bit set. The Host Controller also sets this bit when a short packet is detected, that is, the actual number of bytes received was less than the expected number of bytes. Rev. 02 — 5 March 2007 ISP1561 HS USB PCI Host Controller …continued 111), the Frame Index register rolls over every © ...
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... Frame List Rollover Enable: When this bit and the FLR (Frame List Rollover) bit in the USBSTS register are set, the Host Controller issues an interrupt. The interrupt is acknowledged by software clearing the FLR (Frame List Rollover) bit. Rev. 02 — 5 March 2007 ISP1561 HS USB PCI Host Controller ...
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... R/W R FRINDEX[7: R/W R/W Rev. 02 — 5 March 2007 ISP1561 HS USB PCI Host Controller …continued FRINDEX[13: R/W R/W R R/W R/W R/W © NXP B.V. 2007. All rights reserved. ...
Page 76
... FLS (Frame List Size) field in the USBCMD register. Number elements 1024 512 256 reserved Rev. 02 — 5 March 2007 ISP1561 HS USB PCI Host Controller Table 111 illustrates N based on the value of the © ...
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... HS USB PCI Host Controller R/W R/W R R/W R/W R reserved 114) contains the address of the next R/W R/W R R/W R/W R/W ISP1561 R/W © NXP B.V. 2007. All rights reserved 103 ...
Page 78
... Host Controller. This bit controls the default port-routing control logic. 0 — Port routing control logic default-routes each port to an implementation dependent classic Host Controller 1 — Port routing control logic default-routes all ports to this Host Controller Rev. 02 — 5 March 2007 ISP1561 HS USB PCI Host Controller ...
Page 79
... Wake on Disconnect Enable: Default = 0. Setting this bit enables the port CNNT_E to be sensitive to device disconnects as wake-up events. WKCNNT Wake on Connect Enable: Default = 0. Setting this bit enables the port sensitive to device connects as wake-up events. Rev. 02 — 5 March 2007 ISP1561 HS USB PCI Host Controller Table 118 the ...
Page 80
... J-state: Not a low-speed device, perform EHCI reset 11b — undefined: Not a low-speed device, perform EHCI reset. If Port Power (PP) is logic 0, this field is undefined. Rev. 02 — 5 March 2007 HS USB PCI Host Controller …continued [1] Specification”. ISP1561 Ref. 8 © NXP B.V. 2007. All rights reserved 103 ...
Page 81
... If the host software sets this bit when the Port Enabled bit is logic 0, the results are undefined. Rev. 02 — 5 March 2007 HS USB PCI Host Controller …continued Ref. 8 “Universal Serial Bus Specification” Specification”, is completed. [1] [1] ISP1561 is started. Ref. 8 © NXP B.V. 2007. All rights reserved 103 ...
Page 82
... ECSC (Connect Status Change) bit to be set. Rev. 02 — 5 March 2007 HS USB PCI Host Controller …continued Specification”. The resume signaling (full-speed ‘K’) is Specification”. Software clears [1] ISP1561 Ref. 8 [1] [1] [1] © NXP B.V. 2007. All rights reserved 103 ...
Page 83
... ISP1561 three high-speed devices connected to the ISP1561 four high-speed devices connected to the ISP1561 no devices connected to the ISP1561 one high-speed device connected to the ISP1561 two high-speed devices connected to the ISP1561 three high-speed devices connected to the ISP1561 four high-speed devices connected to the ISP1561 ...
Page 84
... ISP1561_2 Product data sheet …continued Conditions no devices connected to the ISP1561 one high-speed device connected to the ISP1561 two high-speed devices connected to the ISP1561 three high-speed devices connected to the ISP1561 four high-speed devices connected to the ISP1561 Typ 130 [3] 1.5 [4] 0.52 Specification”. Specification”. ...
Page 85
... > all pins (I < [2] on pins DM1 to DM4, DP1 to DP4, and all GND pins (I < Conditions Min 3.0 3.0 3.0 3.0 [ Rev. 02 — 5 March 2007 ISP1561 HS USB PCI Host Controller Min Max Unit 0.5 +4.6 V 0.5 +4.6 V 0.5 +4.6 V 0.5 +4.6 V 0.5 +6.0 V 0.5 +4 100 mA ...
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... C-bus interface (SDA and SCL) Conditions Conditions Conditions 0 V < V < 500 A OUT I = 1500 A OUT Conditions squelch detected no squelch detected Rev. 02 — 5 March 2007 ISP1561 HS USB PCI Host Controller Min Typ Max 2 0.9 0. 0.4 [1] Min Typ Max 2 ...
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... ISP1561_2 Product data sheet Conditions Min disconnect 625 detected disconnect not - detected 50 10 360 10 [1] 700 [1] 900 drive 2 0.8 2.8 0 0.8 1.3 Rev. 02 — 5 March 2007 ISP1561 HS USB PCI Host Controller …continued Typ Max Unit - - mV - 525 mV - +500 440 1100 mV - 500 ...
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... Min Typ Max [ 250 and the maximum rise time (300 ns), use an external OL [1] Min Typ Max [ Min Typ Max 500 - - 500 - - ISP1561 Unit MHz MHz % ppm Unit ns Unit V/ns Unit ps ps © NXP B.V. 2007. All rights reserved 103 ...
Page 89
... Conditions pF pF full-speed timing low-speed timing Conditions Rev. 02 — 5 March 2007 ISP1561 HS USB PCI Host Controller …continued Min Typ Max 40.5 45 49.5 479.76 - 480.24 124.9375 - 125.0625 1 - four high-speed bit times Min ...
Page 90
... REQ# and GNT# are point-to-point signals. GNT# has a setup of 10 ns; REQ# has a setup of 12 ns. All others are bus signals. Fig 5. PCI clock ISP1561_2 Product data sheet Conditions t HIGH 0.6V DD 0.5V DD 0.4V DD 0.3V DD 0.2V DD Rev. 02 — 5 March 2007 ISP1561 HS USB PCI Host Controller Min Typ Max ...
Page 91
... SE0/EOP skew PERIOD DEOP Rev. 02 — 5 March 2007 ISP1561 HS USB PCI Host Controller ; t t su(ptp) h inputs valid 0.615V (falling edge) DD 0.285V (rising edge off source EOP width: t receiver EOP width: t © ...
Page 92
... Rev. 02 — 5 March 2007 HS USB PCI Host Controller detail 0.75 0.95 1 0.2 0.07 0.08 0.45 0.65 EUROPEAN PROJECTION ISP1561 SOT420 ( 0.65 0 ISSUE DATE 99-11-03 03-02-20 © NXP B.V. 2007. All rights reserved 103 ...
Page 93
... Solder bath specifications, including temperature and impurities ISP1561_2 Product data sheet Rev. 02 — 5 March 2007 ISP1561 HS USB PCI Host Controller © NXP B.V. 2007. All rights reserved 103 ...
Page 94
... Package reflow temperature ( C) 3 Volume (mm ) < 350 260 260 250 Figure 10. Rev. 02 — 5 March 2007 ISP1561 HS USB PCI Host Controller Figure 10) than a PbSn process, thus 350 220 220 350 to 2000 > 2000 260 260 250 245 245 245 © ...
Page 95
... PMC PME PMCSR USB VID 20. References [1] Designing a Hi-Speed USB Host PCI Adapter Using the ISP1561 — AN10006 [2] Enhanced Host Controller Interface Specification for Universal Serial Bus — Rev. 095 ISP1561_2 Product data sheet maximum peak temperature = MSL limit, damage level ...
Page 96
... NXP Semiconductors [3] ISP1561 Evaluation Board User’s Guide — UM10005 [4] Open Host Controller Interface Specification for USB — Rev. 1.0a [5] PCI Bus Power Management Interface Specification — Rev. 1.1 [6] PCI Local Bus Specification — Rev. 2.2 [7] The I [8] Universal Serial Bus Specification — Rev. 2.0 ...
Page 97
... LS[1:0]. and Table 115 “ASYNCLISTADDR register and Table 130 “Dynamic SCL)”: updated table title. timing”: updated. and added the max value for ISP1561 description”: 4Ch)”: . cyc © NXP B.V. 2007. All rights reserved 103 ...
Page 98
... Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. GoodLink — trademark of NXP B. C-bus — logo is a trademark of NXP B.V. http://www.nxp.com salesaddresses@nxp.com Rev. 02 — 5 March 2007 ISP1561 HS USB PCI Host Controller © NXP B.V. 2007. All rights reserved 103 ...
Page 99
... Table 91. HceInput register: bit allocation . . . . . . . . . . . . 63 Table 92. HceInput register: bit description . . . . . . . . . . 64 Table 93. HceOutput register: bit allocation . . . . . . . . . . 64 Table 94. HceOutput register: bit description . . . . . . . . . 65 Table 95. HceStatus register: bit allocation . . . . . . . . . . . 65 Rev. 02 — 5 March 2007 ISP1561 HS USB PCI Host Controller continued >> © NXP B.V. 2007. All rights reserved 103 ...
Page 100
... Table 136.SnPb eutectic process (from J-STD-020C .94 ISP1561_2 Product data sheet Table 137.Lead-free process (from J-STD-020C Table 138.Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Table 139.Revision history . . . . . . . . . . . . . . . . . . . . . . . . 97 2 C-bus interface (SDA 2 C-bus interface Rev. 02 — 5 March 2007 ISP1561 HS USB PCI Host Controller continued >> © NXP B.V. 2007. All rights reserved. 100 of 103 ...
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... USB source differential data-to-EOP transition skew and EOP width . . . . . . . . . . . . . . . . . . . . . .91 Fig 9. Package outline SOT420-1 (LQFP128 .92 Fig 10. Temperature profiles for large and small components . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95 ISP1561_2 Product data sheet Rev. 02 — 5 March 2007 ISP1561 HS USB PCI Host Controller continued >> © NXP B.V. 2007. All rights reserved. 101 of 103 ...
Page 102
... HcHCCA register (address: content of the base address register + 18h 11.1.8 HcPeriodCurrentED register (address: content of the base address register + 1Ch 11.1.9 HcControlHeadED register (address: content of the base address register + 20h Rev. 02 — 5 March 2007 ISP1561 HS USB PCI Host Controller continued >> © NXP B.V. 2007. All rights reserved. 102 of 103 ...
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... Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2007. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com ISP1561 All rights reserved. Date of release: 5 March 2007 Document identifier: ISP1561_2 ...