isp1512a NXP Semiconductors, isp1512a Datasheet - Page 31

• Manufacturer Part Number: isp1512a
• Description: Ulpi Hi-speed Usb Transceiver
• Manufacturer: NXP Semiconductors

NXP Semiconductors
Table 34.
Table 35.
Table 36.
Table 37.
ISP1512A_1
Preliminary data sheet
Bit
7 to 0
Bit
Symbol
Reset
Access
Bit
7 to 4
3
2
1 to 0
Bit
Symbol
Reset
Access
Symbol
SCRATCH[7:0]
SCRATCH - Scratch register (address R = 16h to 18h, W = 16h, S = 17h, C = 18h) bit description
CARKIT_CTRL - Carkit Control register (address R = 19h to 1Bh, W = 19h, S = 1Ah, C = 1Bh) bit
allocation
CARKIT_CTRL - Carkit Control register (address R = 19h to 1Bh, W = 19h, S = 1Ah, C = 1Bh) bit
description
PWR_CTRL - Power Control register (address R = 3Dh to 3Fh, W = 3Dh, S = 3Eh, C = 3Fh) bit allocation
Symbol
-
RXD_EN
TXD_EN
-
10.13 SCRATCH register
10.14 CARKIT_CTRL register
10.15 PWR_CTRL register
R/W/S/C
R/W/S/C
7
0
7
0
This is a 1-byte empty register for testing purposes, see
This register controls transparent UART mode. This register is only valid when the
CARKIT_MODE register bit in the INTF_CTRL register is set. When entering UART mode
set the CARKIT_MODE bit, and then set the TXD_EN and RXD_EN bits. After entering
UART mode, the ULPI interface is not available. When exiting UART mode, assert the
STP pin or perform a hardware reset using the CHIP_SEL pin.
For bit allocation, see
This vendor-specific register controls the power feature of the ISP1512A. The bit
allocation of the register is given in
Description
reserved; the link must never write logic 1 to these bits
RXD Enable: Routes the UART RXD signal from the DP pin to the DATA1 pin. This bit will
automatically be cleared when UART mode is exited.
TXD Enable: Routes the UART TXD signal from the DATA0 pin to the DM pin. This bit will
automatically be cleared when UART mode is exited.
reserved; the link must never write logic 1 to these bits
Access
R/W/S/C
R/W/S/C
reserved
R/W/S/C
6
0
6
0
reserved
R/W/S/C
R/W/S/C
Value
00h
5
0
5
0
Table
Rev. 01 — 31 July 2008
Description
Scratch: This is an empty register byte for testing purposes.
Software can read, write, set and clear this register. The functionality
of the PHY will not be affected.
35.
DP_WKPU
R/W/S/C
R/W/S/C
_EN
4
0
4
0
Table
37.
RXD_EN
BVALID_
R/W/S/C
R/W/S/C
FALL
3
0
3
0
BVALID_
TXD_EN
R/W/S/C
R/W/S/C
RISE
Table
2
0
2
0
34.
ULPI HS USB transceiver
R/W/S/C
R/W/S/C
ISP1512A
1
0
1
0
© NXP B.V. 2008. All rights reserved.
reserved
reserved
R/W/S/C
R/W/S/C
0
0
0
0
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