isp1704a NXP Semiconductors, isp1704a Datasheet
isp1704a
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isp1704a Summary of contents
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IMPORTANT NOTICE Dear customer from August 2 2008, the wireless operations of NXP have moved to a new company, ST-NXP Wireless result, the following changes are applicable to the attached document. ● Company name - NXP ...
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... It allows USB Application-Specific Integrated Circuits (ASICs), Programmable Logic Devices (PLDs) or any system chip set to interface with the physical layer of the USB through a 12-pin (SDR) interface. The ISP1704A can interface to devices with digital I/O voltages in the range of 1. 1.95 V. The ISP1704A is available in TFBGA36 package. ...
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... JESD22-A115-A 200 V Machine Model (MM) N JESD22-C101-A 500 V Charge Device Model (CDM) ISP1704A_1 Product data sheet pulsing session request methods BUS voltage comparators BUS Rev. 01 — 28 July 2008 ISP1704A ULPI HS USB transceiver power switch BUS is not present CC(I/O) © NXP B.V. 2008. All rights reserved ...
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... Ordering information Package Name Description TFBGA36 plastic thin fine-pitch ball grid array package; 36 balls; body 3.5 3.5 Marking codes Rev. 01 — 28 July 2008 ISP1704A ULPI HS USB transceiver 3.5 mm) Restriction of Hazardous Substances 0.8 mm [1] Marking code 1704 © NXP B.V. 2008. All rights reserved. Version SOT912-1 ...
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... ISP1704A CLOCK FREQUENCY SELECTION PLL BUFFER interface voltage internal power POWER-ON POR RESET V REF VOLTAGE REGULATOR F1 C5, D2, E4 GND n.c. Rev. 01 — 28 July 2008 ISP1704A ULPI HS USB transceiver D1 DP HI-SPEED USB ATX TERMINATION C1 DM RESISTORS OTG MODULE DETECTOR V BUS COMPARATORS F4 V BUS ...
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... I/O supply voltage 0.1 F decoupling capacitor is recommended for each pin when either the CHIP_SEL or CHIP_SEL_N pin is deasserted, ULPI pins will be in 3-state and the ISP1704A is in power-down mode; both CHIP_SEL and CHIP_SEL_N must be asserted for the ULPI interface to operate normally; when not in use, connect to V ...
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... UART mode: TXD output resistor reference; connect through when either the CHIP_SEL or CHIP_SEL_N pin is deasserted, ULPI pins will be in 3-state and the ISP1704A is in power-down mode; both CHIP_SEL and CHIP_SEL_N must be asserted for the ULPI interface to operate normally; when not in use, connect to GND ...
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... V tolerant; external 100 k pull-down resistor input supply voltage or battery source; 3 4.5 V Remark: Below 3.0 V, USB full-speed and low-speed transactions are not guaranteed to work, though some devices may work with the ISP1704A at these voltages. connect to the V pin of the USB connector; if this pin is not in use, leave it open (an ...
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... NXP Semiconductors 8. Functional description 8.1 ULPI interface controller The ISP1704A provides a 12-pin interface that is compliant with UTMI+ Low Pin Interface (ULPI) Specification Rev. 1.1 . This interface must be connected to a USB link. The ULPI interface controller provides the following functions: • ULPI-compliant interface and register set • ...
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... 8.5 PLL The ISP1704A has a built-in Phase-Locked Loop (PLL) for internal clock generation. The clock frequencies supported are 19.2 MHz and 26 MHz. The PLL takes the square wave clock, and multiplies or divides it into various frequencies for internal use. The PLL produces the following frequencies, irrespective of the clock source: • ...
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... NXP Semiconductors When the ISP1704A is put into UART mode, it acts as a voltage level shifter between the following pins: • From DATA0 (V • From DP (2.7 V level) to DATA1 (V 8.7 OTG module This module contains several sub-blocks that provide all the functionality required by the USB OTG specification. Specifically, it provides the following circuits: • ...
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... Port power control For an OTG or host application, the ISP1704A uses the PSW pin to control the external power switch for the V power switch can be connected to the FAULT pin of the ISP1704A to indicate to the ULPI link the V When the FAULT pin is not used, connect it to GND. ...
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... ULPI interface pins will be put in 3-state, the internal regulator will be shut down, and the total current consumption in power-down mode will be less than that in low-power mode. The link can do a hardware reset to the ISP1704A by powering down the regulator, see Table 4. ...
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... CC(I/O) deasserted Chip select turns from deassert to assert. The ISP1704A regulator starts to turn on. ULPI pads are not in 3-state and may drive to either LOW or HIGH recommended that the link ignores the status of ULPI pins during Power-on reset threshold is reached and the POR pulse is generated. After the POR pulse, ULPI pins are driven to a defi ...
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... Interface behavior with respect to chip select The use of chip select as a power-down control signal is optional. When chip select is deasserted, the ISP1704A will 3-state ULPI pins and power-down the internal circuitry. If chip select is not used as a power-down control signal, it must be connected to LOW. ...
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... USB signal quality. 8.12.4 DP and DM When the ISP1704A is in USB mode, the DP pin functions as the USB data plus line, and the DM pin functions as the USB data minus line. When the ISP1704A is in transparent UART mode, the DP pin functions as the UART RXD input pin, and the DM pin functions as the UART TXD output pin ...
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... The ISP1704A provides an internal pull-up resistor (R pin. The pull-up resistor must first be enabled by setting the ID_PULLUP register bit to logic 1. If the state of ID has changed, the ISP1704A will send an RXCMD or interrupt to the link. If the link does not receive any RXCMD or interrupt by time t has not changed ...
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... By default, the ISP1704A holds DIR at LOW, causing the data bus input. When DIR is LOW, the ISP1704A listens for data from the link. The ISP1704A pulls DIR to HIGH only when it has data to send to the link, which is for one of two reasons: • ...
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... ISP1704A, NXT will be asserted to notify the link to provide the next data byte. When DIR is HIGH and the ISP1704A is sending data to the link, NXT will be asserted to notify the link that another valid byte is on the bus. NXT is not used for register read data or the RXCMD status update ...
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... When V ISP1704A, the application system must detect the low voltage condition and set chip select to deassert (that is, put the ISP1704A in power-down mode). This is to protect the ULPI and USB interfaces from driving wrong levels. Under this condition, the V voltage will not leak to USB pins (V pins powered by V driven to a defi ...
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... The ISP1704A provides the USB charger detection function that complies with USB Battery Charging Specification Rev. 1.0 . The ISP1704A implements the USB charger detection circuit as a peripheral. When the ISP1704A is used as a USB peripheral, it can distinguish between high-current charger (up to 1.8 A) and a standard USB host or hub (up to 500 mA) ...
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... Setting more than one mode will lead to undefined behavior. 9.2.1 Synchronous mode This is default mode. On power-up, and when CLOCK is stable, the ISP1704A will enter synchronous mode. In synchronous mode, the link must synchronize all ULPI signals to CLOCK, meeting the set-up and hold times as defi ...
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... LOW, the ISP1704A asserts NXT to notify the link to place the next data byte on DATA[7:0] in the following clock cycle. If DIR is HIGH, the ISP1704A asserts NXT to notify the link that a valid USB data byte is on DATA[7:0] in the current cycle. The ISP1704A always drives an RXCMD when DIR is HIGH and NXT is LOW, unless register read data returned to the link in the current cycle ...
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... If the link requires a 6-pin serial interface to transmit and receive full-speed or low-speed USB data, it can set the ISP1704A to 6-pin serial mode. In 6-pin serial mode, the data bus definition changes to that shown in 6PIN_FSLS_SERIAL bit in the INTF_CTRL register (see 6-pin serial mode, the link asserts the STP signal ...
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... DATA3 Reserved DATA[7:4] [ input output; I/O = digital input/output. 9.2.5 Transparent UART mode In transparent UART mode, the ISP1704A functions as a voltage level shifter between following pins: • From pin DATA0 (V • From pin DP (2.7 V level) to pin DATA1 (V The USB transceiver is used to drive the UART transmitting signal on the DM line. The rise time and the fall time of the transmitting signal is determined by whether a full-speed or low-speed transceiver is in use ...
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... UART mode is enabled. 2. The 39 3. One clock cycle after DIR goes from LOW to HIGH, the ISP1704A will drive the data bus for five clock cycles. This is to charge the DATA0 pin to a HIGH level for a slow link ...
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... Interface behavior when entering UART mode (1) (2) UART mode signals DIR STP NXT UART mode Rev. 01 — 28 July 2008 ISP1704A ULPI HS USB transceiver turnaround 0001 0001 UART mode signals turnaround synchronous 0000 0000 mode signals © NXP B.V. 2008. All rights reserved. ...
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... A Hi-Speed USB peripheral, host or OTG device handles more than one electrical state as defined in Universal Serial Bus Specification Rev. 2.0 and On-The-Go Supplement to the USB 2.0 Specification Rev. 1.3 . The ISP1704A accommodates various states through register settings of the XCVRSELECT[1:0], TERMSELECT, OPMODE[1:0], DP_PULLDOWN and DM_PULLDOWN bits. ...
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... Rev. 01 — 28 July 2008 ISP1704A ULPI HS USB transceiver …continued Internal resistor settings DM_ RPU_DP RPD_DP RPD_ PULL _EN _EN DM_EN DOWN ...
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... Vendor ID Low: Lower byte of the NXP vendor ID supplied by USB-IF; fixed value of CCh shows the bit description of the register. Value Description 04h* Vendor ID High: Upper byte of the NXP vendor ID supplied by USB-IF; fixed value of 04h Rev. 01 — 28 July 2008 ISP1704A ULPI HS USB transceiver References [3] [ Section 10 ...
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... Value Description 17h* Product ID High: Upper byte of the NXP product ID number; fixed value of 17h Table 20 RESET OPMODE[1: R/W/S/C R/W/S/C Rev. 01 — 28 July 2008 ISP1704A ULPI HS USB transceiver Table 18. Table 19 TERM XCVRSELECT[1:0] SELECT R/W/S/C R/W/S/C R/W/S/C © NXP B.V. 2008. All rights reserved. ...
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... THRU Reset 0 Access R/W/S/C R/W/S/C ISP1704A_1 Product data sheet Table 22 provides the bit allocation of the register IND_ reserved COMPL R/W/S/C R/W/S/C Rev. 01 — 28 July 2008 ISP1704A ULPI HS USB transceiver Table 3 2 CLOCK_ CARKIT_ 3PIN_ SUSPENDM MODE FSLS_ SERIAL 0 0 R/W/S/C R/W/S/C R/W/S/C high-speed 14 6PIN_ FSLS_ ...
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... INTF_PROT_DIS Interface Protect Disable: Controls circuitry built into the ISP1704A to protect the ULPI interface when the link 3-states STP and DATA[7:0]. When this bit is enabled, the ISP1704A will automatically detect when the link stops driving STP. 0b — Enables the interface protect circuit. The ISP1704A attaches a weak pull-up resistor on STP ...
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... DISCHRG_VBUS), and that both the DP and BUS BUS BUS : Discharges V through a resistor. If the link sets this bit to logic 1, it waits BUS BUS BUS BUS Table 26 shows the bit allocation of the register. Rev. 01 — 28 July 2008 ISP1704A ULPI HS USB transceiver DISCHRG_ DM_PULL DP_PULL VBUS DOWN DOWN 0 1 ...
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... Product data sheet ID_GND_R R/W/S/C R/W/S/C Valid Rise: Enables interrupts and RXCMDs for logic 0 to logic 1 transitions on Table 28 ID_GND_F R/W/S/C R/W/S/C Rev. 01 — 28 July 2008 ISP1704A ULPI HS USB transceiver SESS_ SESS_ VBUS_ END_R VALID_R VALID_R R/W/S/C R/W/S/C R/W/S SESS_ SESS_ VBUS_ ...
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... HOST_DISCON 10.11 USB_INTR_L register The bits of the USB_INTR_L register are automatically set by the ISP1704A when an unmasked change occurs on the corresponding interrupt source signal. The ISP1704A will automatically clear all bits when the link reads this register, or when the PHY enters low-power mode. ...
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... Description 00h Scratch: This is an empty register byte for testing purposes. Software can read, write, set and clear this register. The functionality of the PHY will not be affected. Rev. 01 — 28 July 2008 ISP1704A ULPI HS USB transceiver Table 34. This register indicates the ...
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... PWR_CTRL register This vendor-specific register controls the power feature of the ISP1704A. The bit allocation of the register is given in Table 39. PWR_CTRL - Power Control register (address R = 3Dh to 3Fh 3Dh 3Eh 3Fh) bit allocation ...
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... BVALID Fall: Enables RXCMDs for HIGH-to-LOW transitions on BVALID. When BVALID changes from FALL HIGH to LOW, the ISP1704A will send an RXCMD to the link with the ALT_INT bit set to logic 1. This bit is optional and is not necessary for OTG devices. This bit is provided for debugging purposes. ...
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... The ISP1704A has been tested according to the additional requirements listed in Universal Serial Bus Specification Rev. 2.0, Section 7.1.1 . The AC stress test was performed for 24 hours. The ISP1704A was found to be fully operational after the test completed. The ISP1704A was found to be fully functional after shorting the high-speed DP and DM pins to ground for 24 hours. Transmit and receive were occurring the time ...
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... PSW, FAULT, V and BUS CHGR_DET_EN_N on pins STP, DATA[7:0], CFG1, CHIP_SEL, CHIP_SEL_N and TEST_N on pins DP, DM and ID on pin CLKIN Rev. 01 — 28 July 2008 ISP1704A ULPI HS USB transceiver Min Typ Max 3.0 3.6 4.5 is 2.4 3.6 4 ...
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... ULPI bus idle load on pin CLOCK = +85 C; unless otherwise specified. amb = 1 +25 C; unless otherwise specified. CC(I/O) amb Conditions 0 CC(I/ 0 Rev. 01 — 28 July 2008 ISP1704A ULPI HS USB transceiver Min Typ 750 - 600 - 5 ...
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... +85 C; unless otherwise specified. amb = 1 +25 C; unless otherwise specified. CC(I/O) amb Conditions includes V range DI Rev. 01 — 28 July 2008 ISP1704A ULPI HS USB transceiver Min Typ Max ...
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... DP and DM GND L excluding the first transition from the idle state for 1.5 k pull-up resistor bit DP_WKPU_EN = 1b and V > V BUS A_SESS_VLD includes V range DI pin to GND steady-state drive Rev. 01 — 28 July 2008 ISP1704A ULPI HS USB transceiver Min Typ Max Unit 0.0 - 0.3 V 2.8 - 3.6 V 1.3 - 2.0 V 3.0 - 3.6 ...
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... V lost (power-down mode) V lost (power-down CC(I/O) mode +85 C; unless otherwise specified. amb = 1 +25 C; unless otherwise specified. CC(I/O) amb Conditions bit ID_PULLUP = 1b bit ID_PULLUP = 0b Rev. 01 — 28 July 2008 ISP1704A ULPI HS USB transceiver Min Typ Max 40 0.8 2.35 - ...
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... C to +85 C; unless otherwise specified. amb = 1 +25 C; unless otherwise specified. CC(I/O) amb Conditions SUSPENDM = 1b SUSPENDM = 1b; not in UART mode SUSPENDM = 1b; in UART mode = +85 C; unless otherwise specified. amb Conditions Rev. 01 — 28 July 2008 ISP1704A ULPI HS USB transceiver Min Typ Max 1.65 1.8 1.95 V 0.08 3.3 3.6 CC 2.5 2.77 2.9 ...
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... C to +85 C; unless otherwise specified. amb = 1 +25 C; unless otherwise specified. CC(I/O) amb Conditions CLOCK pin transitioning between (20 pF CC(I/O) load) CLOCK pin transitioning between (20 pF CC(I/O) load) Rev. 01 — 28 July 2008 ISP1704A ULPI HS USB transceiver Min Typ Max 0 640 - ...
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... GND on pins DP and pF pF excluding the first transition from the FR FF idle state Rev. 01 — 28 July 2008 ISP1704A ULPI HS USB transceiver Min Typ Max 59.970 60.000 60.030 - - 500 Min ...
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... C to +85 C; unless otherwise specified. amb Conditions TX_DAT, TX_SE0 to DP, DM; see Figure 12 TX_DAT, TX_SE0 to DP, DM; see Figure 12 TX_ENABLE to DP, DM; see TX_ENABLE to DP, DM; see TX_ENABLE to DP, DM; see Rev. 01 — 28 July 2008 ISP1704A ULPI HS USB transceiver …continued Min Typ Max 75 - 300 ...
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... Fig 12. Timing of TX_DAT and TX_SE0 to DP and DM differential data lines 0 PHZ t PLZ V 0 logic output 004aaa574 Fig 14. Timing of DP and DM to RX_RCV, RX_DP and Rev. 01 — 28 July 2008 ISP1704A ULPI HS USB transceiver …continued Min Typ - - - - - - - - 0 PLH(drv) differential V CRS data lines 2 ...
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... C; unless otherwise specified. CC(I/O) amb Conditions activates charger BUS detection BUS BUS resistance between V and pin CHGR_DET at I DAT_SRC V DM BUS , triggering can occur anywhere between 0 4.0 V. When CC O(REG3V3) Rev. 01 — 28 July 2008 ISP1704A ULPI HS USB transceiver t d(o) t d(o) t d(o) Min 4.4 0.8 [ 0.5 0.25 ...
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... DPSRC_HICRNT V attached to charger detect time BUS min = 145 ms HWDETECT bit set in register and read by ULPI in normal mode Rev. 01 — 28 July 2008 ISP1704A ULPI HS USB transceiver V > 0.8 V th(trig)r(VBUS) If charger is detected, then CHGR_DET is held HIGH until V falls below V BUS th(f)(VBUS) or reset by the register setting © ...
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... ESR capacitor (0 for best performance ISP1704A standalone: ESD IEC 61000-4-2 level 4; 8.8kV contact; 17.6kV air discharge compliant protection ISP1704A and IP4359CX4/LF (WLCSP) together: ESD IEC 61000-4-2 level 4; 20kV contact; 40kV air discharge compliant protection © NXP B.V. 2008. All rights reserved. ...
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... STANDARD-B RECEPTACLE A1 5 SHIELD IP4359CX4/ SHIELD 7 SHIELD 8 SHIELD PMU C VBUS C bypass (1) Connect to either GND depending on the clock frequency used. See CC(I/O) Fig 17. Using the ISP1704A with a standard USB peripheral controller CC(I/O) C bypass F3 C4 TEST_N V CHIP_SEL_N CC C bypass B5 V CLOCK CC(I/ ...
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... D+ USB 4 STANDARD-A GND RECEPTACLE 5 SHIELD 6 SHIELD 7 SHIELD 8 SHIELD R pulldown C VBUS C bypass (1) Connect to either GND depending on the clock frequency used. See CC(I/O) Fig 18. Using the ISP1704A with a standard USB host controller bypass CC(I/ TEST_N C bypass B5 V CC(I/ CC(I/O) R RREF C2 RREF ...
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... USB 4 MICRO-AB ID RECEPTACLE 5 GND 6 SHIELD 7 SHIELD 8 SHIELD R pulldown C VBUS C bypass (1) Connect to either GND depending on the clock frequency used. See CC(I/O) Fig 19. Using the ISP1704A with a USB OTG controller bypass CC(I/ TEST_N C bypass B5 V CC(I/ CC(I/O) R RREF C2 RREF C1 ...
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... 3.6 3.6 0.5 2.5 2.5 0.15 3.4 3.4 REFERENCES JEDEC JEITA - - - - - - Rev. 01 — 28 July 2008 ISP1704A ULPI HS USB transceiver detail 0.05 0.08 0.1 EUROPEAN PROJECTION SOT912-1 y ISSUE DATE 05-08-09 05-09-01 © NXP B.V. 2008. All rights reserved ...
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... Solder bath specifications, including temperature and impurities ISP1704A_1 Product data sheet Rev. 01 — 28 July 2008 ISP1704A ULPI HS USB transceiver © NXP B.V. 2008. All rights reserved ...
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... Lead-free process (from J-STD-020C) Package reflow temperature ( C) 3 Volume (mm ) < 350 260 260 250 Figure 21. Rev. 01 — 28 July 2008 ISP1704A ULPI HS USB transceiver Figure 21) than a SnPb process, thus 350 220 220 350 to 2000 > 2000 260 260 250 245 245 245 © ...
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... Host Negotiation Protocol International Electrotechnical Commission Machine Model Non-Return to Zero Inverted On-The-Go Personal Digital Assistant Physical Packet Identifier Phase-Locked Loop Power-On Reset Rev. 01 — 28 July 2008 ISP1704A ULPI HS USB transceiver peak temperature time 001aac844 © NXP B.V. 2008. All rights reserved ...
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... Transmit Data Universal Asynchronous Receiver-Transmitter UTMI+ Low Pin Interface Universal Serial Bus USB Implementers Forum USB Transceiver Macrocell Interface USB Transceiver Macrocell Interface Plus Wafer-Level Chip-Scale Package Rev. 01 — 28 July 2008 ISP1704A ULPI HS USB transceiver © NXP B.V. 2008. All rights reserved ...
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... Electrostatic discharge immunity test (IEC 61000-4-2) 21. Revision history Table 64. Revision history Document ID Release date ISP1704A_1 20080728 ISP1704A_1 Product data sheet Data sheet status Change notice Product data sheet - Rev. 01 — 28 July 2008 ISP1704A ULPI HS USB transceiver Supersedes - © NXP B.V. 2008. All rights reserved ...
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... Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. http://www.nxp.com salesaddresses@nxp.com Rev. 01 — 28 July 2008 ISP1704A ULPI HS USB transceiver © NXP B.V. 2008. All rights reserved ...
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... Table 59. Dynamic characteristics: USB charger detection . . . . . . . . . . . . . . . . . . 50 Table 60. Recommended bill of materials . . . . . . . . . . . . 52 Table 61. SnPb eutectic process (from J-STD-020C Table 62. Lead-free process (from J-STD-020C Table 63. Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Table 64. Revision history . . . . . . . . . . . . . . . . . . . . . . . . 61 Rev. 01 — 28 July 2008 ISP1704A ULPI HS USB transceiver . . . . . . 44 BUS © NXP B.V. 2008. All rights reserved ...
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... Fig 14. Timing of DP and DM to RX_RCV, RX_DP and RX_DM . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 Fig 15. ULPI timing interface . . . . . . . . . . . . . . . . . . . . . .50 Fig 16. Charger detection . . . . . . . . . . . . . . . . . . . . . . . .51 Fig 17. Using the ISP1704A with a standard USB peripheral controller . . . . . . . . . . . . . . . . . . . . . . .53 Fig 18. Using the ISP1704A with a standard USB host controller . . . . . . . . . . . . . . . . . . . . . . . . . . .54 Fig 19. Using the ISP1704A with a USB OTG controller ...
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... Application information . . . . . . . . . . . . . . . . . 52 16 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 56 17 Soldering of SMD packages . . . . . . . . . . . . . . 57 17.1 Introduction to soldering 17.2 Wave and reflow soldering . . . . . . . . . . . . . . . 57 17.3 Wave soldering 17.4 Reflow soldering Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 59 19 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 20 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Rev. 01 — 28 July 2008 ISP1704A ULPI HS USB transceiver continued >> © NXP B.V. 2008. All rights reserved ...
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... Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2008. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com ISP1704A All rights reserved. Date of release: 28 July 2008 Document identifier: ISP1704A_1 ...