isp1705 NXP Semiconductors, isp1705 Datasheet - Page 17

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isp1705

Manufacturer Part Number
isp1705
Description
Ulpi Hi-speed Usb Transceiver
Manufacturer
NXP Semiconductors
Datasheet

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NXP Semiconductors
ISP1705_1
Product data sheet
Fig 8.
CHIP_SEL_N
DATA[7:0]
CLOCK
NXT
Interface behavior with respect to chip select
STP
DIR
8.12.1 DATA[7:0]
8.12.2 V
8.12 Detailed description of pins
Hi-Z (input)
Hi-Z (input)
Bidirectional data bus pins. The USB link must drive DATA[7:0] to LOW when the ULPI bus
is idle. When the link has data to transmit to the PHY, it drives a nonzero value. Weak
pull-down resistors are incorporated into DATA[7:0] pins as part of the interface protect
feature. For details, see
DATA[7:0] pins can also be 3-stated when chip select is deasserted.
These pins can be reconfigured to carry various data types when the chip is not in
synchronous mode. For details, see
The input supply power pin that sets the I/O voltage level. A 0.1 F decoupling capacitor is
recommended on each V
CC(I/O)
CFG1
CFG2
CHIP_SEL
CHIP_SEL_N
CLOCK
DATA[7:0]
DIR
NXT
STP
RESET_N
Rev. 01 — 13 June 2008
Section
CC(I/O)
pin. V
8.11.1.
Section
CC(I/O)
powers the on-chip pads of the following pins:
9.2.
Hi-Z (ignored)
Hi-Z
Hi-Z (ignored)
Hi-Z
t
PWRDN
ULPI Hi-Speed USB transceiver
Hi-Z (ignored)
© NXP B.V. 2008. All rights reserved.
ISP1705
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