s1r72803 Epson Electronics America, Inc., s1r72803 Datasheet - Page 28

• Manufacturer Part Number: s1r72803
• Description: Link/transaction Controller
• Manufacturer: Epson Electronics America, Inc.

S1R72803F00A
24
LinkChnnel Index/Window Register
Address Register Name
ChnlIndex
0x60
0x61
0x62
0x63
0x64
0x65
0x66
0x67
0x68
0x69
0x6A
0x6B
0x6C
0x6D
0x6E
0x6F
0x70
0x71
0x72
0x73
0x74
0x75
0x76
0x77
0x78
0x79
0x7A
0x7B
0x7C
0x7D
0x7E
0x7F
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
IDE_Config0
IDE_Config1
IDE_RegAccCyc
IDE_PioDmaCyc
IDE_UltraDmaCyc
IDE_DmaCtl
IDE_BusStat
IDE_DmaStat
IDE_ByteCount0
IDE_ByteCount1
IDE_ByteCount2
IDE_ByteCount3
IDE_CRC0
IDE_CRC1
IDE_TestIndex
IDE_TestWindow
IDE_CS00
IDE_CS01
IDE_CS02
IDE_CS03
IDE_CS04
IDE_CS05
IDE_CS06
IDE_CS07
IDE_CS10
IDE_CS11
IDE_CS12
IDE_CS13
IDE_CS14
IDE_CS15
IDE_CS16
IDE_CS17
ChannelAvailableH0
ChannelAvailableH1
ChannelAvailableH2
ChannelAvailableH3
ChannelAvailableL0
ChannelAvailableL1
ChannelAvailableL2
ChannelAvailableL3
ReceiveChannel0
ReceiveChannel1
ReceiveChannel2
ReceiveChannel3
ReceiveChannel4
ReceiveChannel5
ReceiveChannel6
ReceiveChannel7
ChnlWindow
UltraDmaMode DmaMode
Command Block register
Command Block register
Command Block register
Command Block register
Command Block register
Command Block register
Command Block register
Command Block register
Control Block Register
Control Block Register
Control Block Register
Control Block Register
Control Block Register
Control Block Register
Control Block Register
Control Block Register
IDE_Reset
DMARQ
(MSB)
(MSB)
bit7
bit7
ch08
ch16
ch24
ch32
ch40
ch48
ch56
ch00
ch08
ch16
ch24
ch32
ch40
ch48
ch56
FIFOCnt[2:0]
DMACK
bit6
ch01
ch09
ch17
ch25
ch33
ch41
ch49
ch57
ch01
ch09
ch17
ch25
ch33
ch41
ch49
ch57
bit6
Assert Pulse[3:0]
Assert Pulse[3:0]
IncFIFOCnt
ActPort
INTRQ
bit5
ch18
ch26
ch34
ch42
ch50
ch58
bit5
ch02
ch10
ch18
ch26
ch34
ch42
ch50
ch58
ch02
ch10
EPSON
R- Data
R- Error
R- Sector Count
R- Sector Number/LBA[bit0-7]
R- Cylinder Low/LBA[bit8-15]
R- Cylinder High/LBA[bit[16-23]
R- Device/Head,LBA[bit24-27]
R- Status
R- Data Bus Hi-Impedence
R- Data Bus Hi-Impedence
R- Data Bus Hi-Impedence
R- Data Bus Hi-Impedence
R- Data Bus Hi-Impedence
R- Data Bus Hi-Impedence
R- Alternate Status
R- (obsolete)
CRC_Clear
IDE_Slave DMARQ_Leve
IDE DMA xfer Byte Count
IORDY
Ultra DMA CRC Value
bit4
ch03
ch11
ch19
ch27
ch35
ch43
ch51
ch59
ch03
ch11
ch19
ch27
ch35
ch43
ch51
ch59
bit4
Chip Test Register
FIFO_Clear
bit3
bit3
ch04
ch12
ch20
ch28
ch36
ch44
ch52
ch60
ch04
ch12
ch20
ch28
ch36
ch44
ch52
ch60
XDIOW_DLYen
IDE_Abort
bit2
ch05
ch13
ch21
ch29
ch37
ch45
ch53
ch61
ch05
ch13
ch21
ch29
ch37
ch45
ch53
ch61
bit2
Swap
Negate Pulse[3:0]
Negate Pulse[3:0]
Cycle Time[3:0]
W- Data
W- Features
W- Sector Count
W- Sector Number/LBA[bit0-7]
W- Cylinder Low/LBA[bit8-15]
W- Cylinder High/LBA[bit[16-23]
W- Device/Head,LBA[bit24-27]
W- Command
W- Not Used
W- Not Used
W- Not Used
W- Not Used
W- Not Used
W- Not Used
W- Device Control
W- Not Used
IDE_Directio
DmaPause
bit1
ch06
ch14
ch22
ch30
ch38
ch46
ch54
ch62
ch06
ch14
ch22
ch30
ch38
ch46
ch54
ch62
bit1
DIAG
DmaStart
DmaRun
DASP
bit0
(LSB)
(LSB)
bit0
ch07
ch15
ch23
ch31
ch39
ch47
ch55
ch63
ch07
ch15
ch23
ch31
ch39
ch47
ch55
ch63