s1r72803 Epson Electronics America, Inc., s1r72803 Datasheet - Page 42

• Manufacturer Part Number: s1r72803
• Description: Link/transaction Controller
• Manufacturer: Epson Electronics America, Inc.

S1R72803F00A
38
Address
0x60
0x61
0x62
0x63
0x64
0x65
0x66
0x67
IDE_Config0
IDE_Config1
IDE_RegAccCyc 7: Assert Pulse[3]
IDE_PioDmaCyc 7: Assert Pulse[3]
IDE_UltraDmaCyc 7:
IDE_DmaCtl
IDE_BusStat
IDE_DmaStat
Register Name
7: UltraDmaMode
6: DmaMode
5: ActPort
4: IDE_Slave
3: DMARQ_Level
2: Swap
1:
0:
7: IDE_Reset
6:
5:
4:
3:
2: XDIOW_DLYen R/W
1:
0:
6: Assert Pulse[2] R/W IDE Register Access Strobe Signal Assert Pulse
5: Assert Pulse[1]
4: Assert Pulse[0]
3: Negate Pulse[3]
2: Negate Pulse[2] R/W IDE Register Access Strobe Signal Negate Pulse
1: Negate Pulse[1]
0: Negate Pulse[0]
6: Assert Pulse[2] R/W IDE Transfer Mode Strobe Signal Assert Pulse
5: Assert Pulse[1]
4: Assert Pulse[0]
3: Negate Pulse[3]
2: Negate Pulse[2] R/W IDE Transfer Mode Strobe Signal Negate Pulse
1: Negate Pulse[1]
0: Negate Pulse[0]
6:
5:
4:
3: Cycle Time[3]
2: Cycle Time[2]
1: Cycle Time[1]
0: Cycle Time[0]
7:
6:
5: IncFIFOCnt
4: CRC_Clear
3: FIFO_Clear
2: IDE_Abort
1: IDE_Direction
0: DmaStart
7: DMARQ
6: DMACK
5: INTRQ
4: IORDY
3:
2:
1: DIAG
0: DASP
7: FIFOCnt[2]
6: FIFOCnt[1]
5: FIFOCnt[0]
4:
3:
2:
1: DmaPause
0: DmaRun
Bit Symbol
R/W
R/W 0: Master
R/W 0: None
R/W IDE Ultra DMA Transfer Mode Strobe Signal
R/W 0: SRAM –> IDE
W
W
W
W
W
W
R
R
R
R
R
0: DMA Mode
0: PIO Mode
0: None
0: Positive Logic
0: Nomal
0:
0:
0:
0:
0:
0:
0: None
0:
0:
Width Minimum Value
Width Minimum Value
Width Minimum Value
Width Minimum Value
0:
0:
0:
0:
Minimum Cycle Time
0:
0:
0: None
0: None
0: None
0: None
0: None
Indicate IDE I/F Signals State
Indicate word count in FIFO
0:
0:
0:
0: IDE DMA not Pause 1: IDE DMA Pause
0: Not DMA
EPSON
Description
1: Ultra DMA Mode
1: DMA Mode
1: Active
1: Slave
1: Negative Logic
1: Swap IDE Port Hi & Lo
1:
1:
1: IDE Reset
1:
1:
1:
1:
1: Delay XDIOW
1:
1:
1:
1:
1:
1:
1:
1:
1: Push FIFO Data
1: CRC Clear
1: FIFO Clear
1: IDE Transfer Abort
1: IDE –> SRAM
1: IDE DMA Start
1:
1:
1:
1: IDE DMA Running
H.Rst S.Rst B.Rst
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
–
–
–
–
–
–
–
–