s1r72803 Epson Electronics America, Inc., s1r72803 Datasheet - Page 76

• Manufacturer Part Number: s1r72803
• Description: Link/transaction Controller
• Manufacturer: Epson Electronics America, Inc.

S1R72803F00A
Buffer Monitor Register
bit7 Rx Payload Ready
bit6 Tx Payload Ready
bit5 Reserved
bit4 TxStreamFull
bit3 Received Header Remain
Bit2 Received ORB Data Full
Bit1 Received Stream Data Full
Bit0 Received Header Full
72
Address
0x51
This Buffer Monitor Register indicates each buffer area status.
This register is read-only. Writing to this register is ignored..
When a free space the equivalent of the size set by the PyloadSize Register exists in the RxStreamArea, this bit
becomes “1”. When not, this bit becomes “0”.
When transmit data the equivalent of the size set by the PayloadSize Register is accumulated in the
RxStreamArea, this bit becomes “1”. When not, this bit becomes “0”.
This bit indicates the status of the transmitting stream buffer. This bit becomes “1” when the buffer is full, and
“0” in other statuses.
When an unused packet header exists in the header area of a receive packet, this bit becomes “1”.
When the firmware rewrites the UsedRxHdrPtr to one same as LINKRxHdrPtr or when you write “1” to the
BufControl.RxHdrCtr bit, this bit becomes “0”.
When the ORB buffer area of receive packet data is full of received data, this bit becomes “1”. The firmware
must turn on RxDMACtl.ForceBusy bit if this bit is turned on to give priority to the processing to free the buffer
by starting a processing with the first received packet immediately. When the receive buffer area is freed, the
RxDMACtl.ForceBusy is cleared.
When the stream buffer area of receive packet data is full of received data, this bit becomes “1”. The firmware
must turn on the RxDMACtl.ForceBusy bit if this bit is turned on to give priority to the processing to free the
buffer by starting a processing with the first received packet immediately. When the receive buffer area is freed,
the RxDMACtl.ForceBusy is cleared.
When the header area of receive packet data is full, this bit becomes “1”. The firmware must turn on the
RxDMACtl.ForceBusy bit if this bit is turned on to give priority to the processing to free the buffer by starting
a processing with the first received packet immediately. When the receive buffer area is freed, the
RxDMACtl.ForceBusy is cleared.
Register Name
BufMonitor
7: RxPayldRdy
6: TxPayldRdy
5:
4: TxStreamFull
3: RxHdrRemain
2: RxORBFull
1: RxStreamFull
0: RxHdrFull
Bit Symbol
R/W
R
R
R
R
R
R
R
0: Rx Payld Capa not Ready 1: Rx Payload Capa Ready
0: Tx Payld Capa not Ready 1: Tx Payload Capa Ready
0:
0: NotFull
0: Rx Header Area Empty
0: Rx ORB Area not Full
0: Rx Stream Area not Full
0: Rx Header Area not Full
EPSON
Description
1:
1: Full
1: Rx Header not Empty
1: Rx ORB Data Area Full
1: Rx Stream Data Area Full
1: Rx Header Area Full
H.Rst S.Rst B.Rst
0x00
0x00
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