lan8700 Standard Microsystems Corp., lan8700 Datasheet - Page 52

• Manufacturer Part Number: lan8700
• Description: ?15kv Esd Protected Mii/rmii 10/100 Ethernet Transceiver With Hp Auto-mdix Support And Flexpwrtm Technology In A Small Footprint
• Manufacturer: Standard Microsystems Corp.

Revision 2.0 (07-15-08)
5.4.8
5.4.8.1
5.4.9
5.4.9.1
5.4.9.2
MODE[2:0]
000
001
010
100
011
The Full-Duplex LED output is driven active low when the link is operating in Full-Duplex mode.
Loopback Operation
The 10/100 digital has two independent loop-back modes: Internal loopback and far loopback.
Internal Loopback
The internal loopback mode is enabled by setting bit register 0 bit 14 to logic one. In this mode, the
scrambled transmit data (output of the scrambler) is looped into the receive logic (input of the
descrambler). The COL signal will be inactive in this mode, unless collision test (bit 0.7) is active.
In this mode, during transmission (TX_EN is HIGH), nothing is transmitted to the line and the
transmitters are powered down.
Configuration Signals
The PHY has 11 configuration signals whose inputs should be driven continuously, either by external
logic or external pull-up/pull-down resistors.
Physical Address Bus - PHYAD[4:0]
The PHYAD[4:0] signals are driven high or low to give each PHY a unique address. This address is
latched into an internal register at end of hardware reset. In a multi-PHY application (such as a
repeater), the controller is able to manage each PHY via the unique address. Each PHY checks each
management data frame for a matching address in the relevant bits. When a match is recognized, the
PHY responds to that particular frame. The PHY address is also used to seed the scrambler. In a multi-
PHY application, this ensures that the scramblers are out of synchronization and disperses the
electromagnetic radiation across the frequency spectrum.
Mode Bus – MODE[2:0]
The MODE[2:0] bus controls the configuration of the 10/100 digital block. When the nRST pin is
deasserted, the register bit values are loaded according to the MODE[2:0] pins. The 10/100 digital
block is then configured by the register bit values. When a soft reset occurs (bit 0.15) as described in
Table
MODE[2:0] pins have no affect.
10Base-T Half Duplex. Auto-negotiation disabled.
10Base-T Full Duplex. Auto-negotiation disabled.
100Base-TX Half Duplex. Auto-negotiation
disabled.
CRS is active during Transmit & Receive.
100Base-TX Full Duplex. Auto-negotiation disabled.
CRS is active during Receive.
100Base-TX Half Duplex is advertised. Auto-
negotiation enabled.
CRS is active during Transmit & Receive.
5.30, the configuration of the 10/100 digital block is controlled by the register bit values, and the
MODE DEFINITIONS
±15kV ESD Protected MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support and flexPWR
Table 5.48 MODE[2:0] Bus
DATASHEET
52
DEFAULT REGISTER BIT VALUES
REGISTER 0
[13,12,10,8]
0000
0001
1000
1001
1100
SMSC LAN8700/LAN8700i
TM
REGISTER 4
Technology in a Small Footprint
[8,7,6,5]
0100
N/A
N/A
N/A
N/A
Datasheet