lan91c100 Standard Microsystems Corp., lan91c100 Datasheet - Page 73

• Manufacturer Part Number: lan91c100
• Description: Feast ? Ast Ethernet Controller
• Manufacturer: Standard Microsystems Corp.

nBE0 nBE1
nBE2 nBE3
nRESET
SIGNAL
VL BUS
D0-D31
nLDEV
OPEN
nADS
LCLK
IRQn
GND
VCC
nADS, nCYCLE
INTR0-INTR3
LAN91C100
A1, nVLBUS
nBE0 nBE1
nBE2 nBE3
nRD, nWR
nDATACS
SIGNAL
D0-D31
RESET
nLDEV
LCLK
Table 3 - VL Local Bus Signal Connections
Local Bus Clock. Rising edges used for synchronous bus
interface transactions.
Connected via inverter to the LAN91C100.
Byte enables. Latched transparently by nADS rising edge.
Address Strobe is connected directly to the VL bus. nCYCLE
is created typically by using nADS delayed by one LCLK.
Typically uses the interrupt lines on the ISA edge connector
of VL bus.
32 bit data bus. The bus byte(s) used to access the device
are a function of nBE0-nBE3:
n
Not used = tri-state on reads, ignored on writes. Note that
nBE2 and nBE3 override the value of A1, which is tied low
in this application.
nLDEV is a totem pole output. nLDEV is active on valid
decodes of A15-A4 and AEN=0.
BE0
UNUSED PINS
0
0
1
0
1
1
1
73
BE1 nBE
0
0
1
1
0
1
1
2
0
1
0
1
1
0
1
BE3
NOTES
0
1
0
1
1
1
0
Double word access
Low word access
High word access
Byte 0 access
Byte 1 access
Byte 2 access
Byte 3 access