lan9211 Standard Microsystems Corp., lan9211 Datasheet - Page 44

• Manufacturer Part Number: lan9211
• Description: Lan9211 High-performance Small Form Factor Single-chip Ethernet Controller With Hp Auto-mdix Support
• Manufacturer: Standard Microsystems Corp.

Revision 2.3 (08-06-08)
MAC and Host
Internal Clock
Management
MAC Power
Interface
BLOCK
Device
PHY
Note 3.16 The PME interrupt status bit on the INT_STS register (PME_INT) is set regardless of the
A write to the BYTE_TEST register, regardless of whether a carrier was detected, will return the
LAN9211 to the D0 state and will reset the PM_MODE field to the D0 state. As noted above, the host
is required to check the READY bit and verify that it is set before attempting any other reads or writes
of the device. Before the LAN9211 is fully awake from this state the EDPWRDOWN bit in register 17
of the PHY must be cleared in order to wake the PHY. Do not attempt to clear the EDPWRDOWN bit
until the READY bit is set. After clearing the EDPWRDOWN bit the LAN9211 is ready to resume normal
operation. At this time the WUPS field can be cleared.
setting of PME_EN.
(NORMAL OPERATION)
Full ON
Full ON
Full ON
Full ON
Table 3.10 Power Management States
D0
KEY
CLOCK ON
BLOCK DISABLED – CLOCK ON
FULL OFF
DATASHEET
High-Performance Small Form Factor Single-Chip Ethernet Controller with HP Auto-MDIX Support
44
RX Power Mgmt. Block
Full ON
Full ON
(WOL)
OFF
D1
On
Energy Detect Power-Down
(ENERGY DETECT)
OFF
OFF
OFF
D2
SMSC LAN9211
Datasheet