sdio101 NXP Semiconductors, sdio101 Datasheet
sdio101
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sdio101 Summary of contents
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... V to 3.6 V voltage range. A built-in data buffer allows for a low interrupt latency time and efficient communication with the host processor at high data rates. The SDIO101 provides a DMA request line that can be connected to an external DMA controller to off-load the host processor and increase overall system performance. ...
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... TFBGA64 plastic thin fine-pitch ball grid array package; 64 balls; body 4 × 4 × 0.8 mm HXQFN60U plastic thermal enhanced extremely thin quad flat package; no leads; 60 terminals; UTLP based; body 5 × 5 × 0.5 mm Rev. 03 — 11 March 2010 SDIO101 SD/SDIO/MMC/CE-ATA host controller Ref. 2) Ref. 3) Ref. 4) Ref. ...
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... Fig 1. SDIO101_3 Product data sheet DDA DD(IO) DD SDIO101 16-BIT ASYNCHRONOUS MEMORY INTERFACE POWER MANAGEMENT Block diagram of SDIO101 Rev. 03 — 11 March 2010 SD/SDIO/MMC/CE-ATA host controller V X2_CLK X1_CLK DD(SD) OSCILLATOR PLL ADDITIONAL CLOCK CONTROL SD/SDIO/ MMC/CE-ATA HOST INTERFACE DATA BUFFER 002aae475 SDIO101 ...
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... D10 V D6 DD(IO) D14 D9 GND D5 D11 D12 GND GND D8 V DAT3 RESET CS DD DAT0 V DAT7 POW0 DD(SD) DAT1 DAT4 DAT6 V DD(SD) DAT2 GND DAT5 SDCD Table 1, Table note [1]) SDIO101 DD(IO) POW1 GND SDWP 002aad064 © NXP B.V. 2010. All rights reserved ...
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... A28 A27 A26 A25 B19 B18 B17 B16 D8 B15 B14 SDIO101IHR B13 B12 B11 B10 D7 A12 A13 A14 A15 A16 002aaf243 Transparent top view SDIO101 D4 A24 A23 A22 A21 A20 A19 A18 A17 D3 © NXP B.V. 2010. All rights reserved ...
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... B17 B16 D8 A24 A23 B15 A22 B14 A21 SDIO101IHR B13 A20 B12 A19 B11 A18 A17 B8 B9 B10 D7 A12 A13 A14 A15 A16 D3 002aaf244 SDIO101 GND V DD(IO) CS POW1 RESET POW0 SDWP © NXP B.V. 2010. All rights reserved ...
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... NXP Semiconductors 5.2 Pin description 5.2.1 Pin description by function Following are the signal descriptions on the SDIO101 interfaces. Pins are organized by function. Table 2. Pin description by function B = bidirectional input output; n.c. = not connected. Symbol Pin [1] TFBGA64 HXQFN60U SD/SDIO/MMC/CE-ATA interface signals SDCLK G3 A9 CMD H3 B6 DAT0 ...
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... Address lines. Can be used to address the 256 bytes of the Standard Host register space. I Address 8. When accessing SDIO101 transmit or receive buffer under DMA control, this pin must be HIGH. This pin must be LOW when accessing other registers or when accessing transmit or receive buffer under interrupt control. ...
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... Interrupt mode—address line A8 must be at logic 1 when Buffer Data Ports are being accessed while the rest of the address lines are ignored by the SDIO101. Once the DMA operation starts, all the accesses to the SDIO101 with A8 set to logic 1 will be considered as Buffer Data Ports access. To access other SDIO101 internal registers, address A8 must be set to logic 0 ...
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... DMA burst size programmed in DMA register [9:0]. The DREQ will go LOW once a block of data has been written to the SDIO101’s transmit buffer, and DREQ will remain LOW for a period defined by DMA register bit [15:9]. The DREQ signal will go HIGH again if the transmit buffer still has space to hold at least the burst size of 16-bit word data ...
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... Host Control register will always read zero, and writing to it will have no effect. 6.3.6 Power Control register (offset 0x29) Bits R[03:00] control the POW[1:0] pins of the SDIO101, which can be used to control an external power supply that powers the SD/SDIO/MMC/CE-ATA device. Two power modes are supported: ‘ ...
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... NXP Semiconductors 6.3.7 Capabilities register (offset 0x40) The SDIO101 Capabilities register contents are shown in Table 5. Location 63: 20:18 17:16 15:14 13: 05:00 6.4 Additional register set description The additional registers are not part of the SD Host Standard Specification Version 2.0 (see Ref. software does not have to be aware of them. ...
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... DREQ delay period (DREQ LOW time) LOW time = value × SD clock cycle time R/W 0h DMA burst size (DREQ HIGH time) Section 6.1 for more detailed DMA description. Rev. 03 — 11 March 2010 SDIO101 SD/SDIO/MMC/CE-ATA host controller Table 7 DMA burst size D06 D05 D04 D03 D02 D01 D00 002aad321 © ...
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... SD SLOT 1 CLOCK CONTROL REGISTER divisor DIVIDER f PLL F DIVIDER M (1) F/divisor CONTROLLER N M SECONDARY CLOCK CONTROL REGISTER Equation 1: integer divisor N D09 D08 D07 D06 D05 D04 D03 D02 D01 SDIO101 f SDCLK(base) 002aac758 (1) D00 002aac759 © NXP B.V. 2010. All rights reserved ...
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... Fig 10. X1_CLK connected to processor’s system clock Fig 11. X1_CLK connected to processor crystal clock output Figure 12 clock source, and the same clock is used by the SDIO101 to operate the SD clock as close to 50 MHz as possible. Fig 12. Host processor using 13 MHz crystal as clock source With its input clock supplies by the processor crystal output, the SDIO101 internal PLL ...
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... Figure 13 reserved D15 D14 D13 D12 D11 D10 D09 D08 D07 Rev. 03 — 11 March 2010 SDIO101 SD/SDIO/MMC/CE-ATA host controller and Table 10 below show the register bits of the INT mode slave DMA enable Hibernate mode Coma mode D06 D05 D04 ...
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... PLL register (offset 0xFA) The PLL register is located in the Common register area. This register provides control over the Phase-Locked Loop, which is used in the SDIO101 to generate an SD base clock frequency from the crystal oscillator or external clock source. The default values of this register are such that the PLL multiplies the incoming frequency from the crystal oscillator by 5 ...
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... NXP Semiconductors Fig 14. PLL register Table 11. Location 15 14 13:07 06:05 04:00 6.4.6 Host Controller Version register (offset 0xFE) The SDIO101 Host Controller version is shown in Table 12. Location 15:08 07:00 SDIO101_3 Product data sheet PLL bypass PLL direct reserved D15 D14 D13 D12 D11 D10 D09 D08 D07 Contents of the PLL register (offset 0xFA) ...
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... NXP Semiconductors 6.5 Power-saving modes The SDIO101 provides 5 power-saving modes that can be used in different situations to minimize the power consumption of the device. and their associated register bits that can be programmed to enable them. Idle, Low Power and Standby modes can be used if card interrupts should still be serviced. The Hibernate mode will switch off the power to the SD device and the Coma mode switches off most of the Host Controller, therefore, card interrupts will not be generated ...
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... The SDIO101 provides SD/SDIO/MMC/CE-ATA functionality to a microprocessor system as illustrated in processor will be able to access the standard host register set in the SDIO101 through the 16-bit memory interface, and initiate transactions to and from the SD card. An external SD power supply (controlled by the SDIO101) can be used to supply the SD card. ...
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... V interface operating SD/MMC/SDIO interface; Human Body Model Conditions Min core 1.65 host interface 2.25 SD interface 1.65 [ MHz; - SDCLK = 25 MHz Standby mode - Hibernate mode - Coma mode - −40 Rev. 03 — 11 March 2010 SDIO101 Min Max Unit −0.3 +4.6 V −0.3 +1.95 V −0.3 +3.6 V −0.3 +2.4 V − −0.3 +3.6 V − ...
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... Product data sheet Conditions X1_CLK X1_CLK −800 μ X1_CLK = 3.3 V) DD(SD) 25 MHz 52 MHz 25 MHz 52 MHz 25 MHz 52 MHz = 3.3 V) DD(SD) 25 MHz = 3.3 V) DD(SD Rev. 03 — 11 March 2010 SDIO101 SD/SDIO/MMC/CE-ATA host controller 3.3 V DD(IO) DD(IO) Min Max Min −0.3 −0.3 [1] +0.6 [1] 2.4 V 2.4 DD −0.3 −0.3 +0.65 1 ...
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... Rev. 03 — 11 March 2010 SDIO101 = 2 3.3 V Unit DD(IO) Max Min Max - MHz - ...
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... Conditions 10 pF max max max max max max max. during data transfer mode max. Rev. 03 — 11 March 2010 SDIO101 SD/SDIO/MMC/CE-ATA host controller 25 MHz 52 MHz Min Max Min Max ...
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... Fig 18. 16-bit write SDIO101_3 Product data sheet t h(A) t h(WE-CS w(WE) d(WE) t h(BEn) 10b t t su(D-WEH) h(WEH-D) D[7:0] t h(A) t h(WE-CS w(WE) d(WE) t h(BEn) 00b t t su(D-WEH) h(WEH-D) D[15:0] Rev. 03 — 11 March 2010 SDIO101 SD/SDIO/MMC/CE-ATA host controller 01b D[15:8] 002aad301 00b D[15:0] 002aad302 © NXP B.V. 2010. All rights reserved ...
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... BE0 to BE1 D[15:0] Fig 20. 16-bit read SDIO101_3 Product data sheet t h(A) t h(RE-CS w(RE) d(RE) t h(BEn) 10b t t d(RE-Q) dis(RE-QZ) D[7:0] t h(A) t h(RE-CS w(RE) d(RE) t h(BEn) 00b t t d(RE-Q) dis(RE-QZ) D[15:0] Rev. 03 — 11 March 2010 SDIO101 SD/SDIO/MMC/CE-ATA host controller 01b D[15:8] 002aad304 00b D[15:0] 002aad303 © NXP B.V. 2010. All rights reserved ...
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... Rev. 03 — 11 March 2010 SD/SDIO/MMC/CE-ATA host controller t w(clk 0.7V 0. 0.2V 0. TLH t ISU t IH valid t ODLY(max) valid t w(clk 0.7V 0. 0.2V 0. TLH t ISU t IH valid t OH valid SDIO101 t ODLY(min) 002aad306 002aad305 © NXP B.V. 2010. All rights reserved ...
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... SD/SDIO/MMC/CE-ATA host controller t su(A8) DON'T CARE t su(A8-CS) DMA burst size su(A8) DON'T CARE t su(A8-CS) DMA burst size Rev. 03 — 11 March 2010 SDIO101 t d(SDCLK-DREQH) t d(CSH-DREQL)W DMA inter delay 002aad324 t d(SDCLK-DREQH) t d(CSH-DREQL)R DMA inter delay 002aad325 © NXP B.V. 2010. All rights reserved. ...
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... WE register buffer write ready 0x30 INT t d(buf_emp-INTL WL(X1_CLK) WH(X1_CLK) T X1_CLK Rev. 03 — 11 March 2010 SDIO101 SD/SDIO/MMC/CE-ATA host controller t d(int_clr-INTH) write to interrupt status register to clear t d(int_clr-INTH) write to interrupt status register to clear © NXP B.V. 2010. All rights reserved. 002aad521 002aad522 002aad677 ...
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... 4.1 4.1 0.4 2.8 2.8 0.15 3.9 3.9 REFERENCES JEDEC JEITA - - - - - - Table 1, Table note [1] Rev. 03 — 11 March 2010 SD/SDIO/MMC/CE-ATA host controller detail 0.05 0.08 0.1 EUROPEAN PROJECTION SDIO101 SOT969-1 ISSUE DATE 06-09-22 06-09-27 © NXP B.V. 2010. All rights reserved ...
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... Rev. 03 — 11 March 2010 SD/SDIO/MMC/CE-ATA host controller detail 1 0.25 0.35 0.10 0.35 3.5 0.5 0.20 0.30 0.07 0.30 0.07 0.15 0.25 0.05 0.25 European projection SDIO101 SOT1133 0.05 0.08 0.1 sot1133-1_po Issue date 08-12-17 09-01-22 © NXP B.V. 2010. All rights reserved ...
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... Solder bath specifications, including temperature and impurities SDIO101_3 Product data sheet SD/SDIO/MMC/CE-ATA host controller Rev. 03 — 11 March 2010 SDIO101 © NXP B.V. 2010. All rights reserved ...
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... Lead-free process (from J-STD-020C) Package reflow temperature (°C) 3 Volume (mm ) < 350 260 260 250 Figure 30. Rev. 03 — 11 March 2010 SDIO101 SD/SDIO/MMC/CE-ATA host controller Figure 30) than a SnPb process, thus ≥ 350 220 220 350 to 2000 > 2000 260 260 250 245 ...
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... Product data sheet maximum peak temperature = MSL limit, damage level temperature minimum peak temperature = minimum soldering temperature MSL: Moisture Sensitivity Level Rev. 03 — 11 March 2010 SDIO101 SD/SDIO/MMC/CE-ATA host controller peak temperature time 001aac844 © NXP B.V. 2010. All rights reserved ...
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... Card detection in Hibernate mode or Coma mode Card detection does not work when the device is in Coma mode or Hibernate mode. When put in these modes, the SDIO101 SD supply is powered down. When a card is inserted, the card detection circuit won't be able to detect the card because there is no power. Workaround: If the card put in Hibernate mode or Coma mode, a processor’ ...
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... Document ID Release date SDIO101_3 20100311 • Modifications: Table 1 “Ordering – Removed type number SDIO101IHE (HUQFN60U, SOT1008-1). – Added type number SDIO101IHR (HXQFN60U, SOT1133-1). • Figure 4 “Pin configuration for HXQFN60U” • Figure 5 “Terminal mapping for HXQFN60U” • Table 2 “Pin description by to “ ...
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... In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the Rev. 03 — 11 March 2010 SDIO101 SD/SDIO/MMC/CE-ATA host controller © NXP B.V. 2010. All rights reserved ...
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... For sales office addresses, please send an email to: SDIO101_3 Product data sheet 19.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. http://www.nxp.com salesaddresses@nxp.com Rev. 03 — 11 March 2010 SDIO101 SD/SDIO/MMC/CE-ATA host controller © NXP B.V. 2010. All rights reserved ...
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... Capabilities register (offset 0x40 6.4 Additional register set description 6.4.1 IO Configuration register (offset 0x50 6.4.2 DMA register (offset 0xF4 6.4.3 Secondary Clock Control register (offset 0xF6 6.4.3.1 SDIO101 X1_CLK input . . . . . . . . . . . . . . . . . 15 6.4.4 Miscellaneous register (offset 0xF8 6.4.5 PLL register (offset 0xFA 6.4.6 Host Controller Version register (offset 0xFE 6.5 Power-saving modes . . . . . . . . . . . . . . . . . . . 19 7 Application design-in information ...