m66291 Renesas Electronics Corporation., m66291 Datasheet - Page 34

• Manufacturer Part Number: m66291
• Description: Assp Usb2.0 Device Controller
• Manufacturer: Renesas Electronics Corporation.

M 6 6 2 9 1 G P / H P
2.13 Interrupt Status Register 1
R e v 1 . 0 1
(1) EPB_RDY (Buffer Ready Interrupt) Bits (b6~b0)
15~7
b15
6~0
Interrupt Status Register 1 (INT_STATUS1)
b
0
0
-
Note :
The bit corresponding to each endpoint is set to “1” with the buffer at “ready” state.
The ready state refers to the state when CPU or DMAC can read or write the CPU side buffer. When the EPB_RE
bit is set to “1”, if this bit is set to “1”, the INTR bit is set to “1”, causing the buffer ready interrupt to occur.
Setting “1”/clearing to ”0” to this bit differs according to the endpoint and transfer direction as shown below:
2 0 0 4 . 1 1 . 0 1
Reserved. Set it to “0”.
EPB_RDY
Buffer Ready Interrupt
14
0
0
-
Refer to “3.2 FIFO Buffer” for CPU/SIE side.
Endpoint 0
13
0
0
-
When set to control write transfer (ISEL bit = “0”)
When set to control read transfer (ISEL bit = “1”)
The condition for this bit to be set to “1” is as follows:
The condition for this bit to be cleared to “0” differs according to the RDYM bit:
This bit is not set to “1” (Refer to “EPB_EMP_OVR bit”).
p a g e 3 4 o f 1 2 2
•
•
•
12
0
0
-
Bit name
When the IVAL bit of the EP0_FIFO Control Register changes from “0” to “1”
RDYM bit = “0” : When the IVAL bit of the EP0_FIFO Control Register changes from
RDYM bit = “1” : Writes “0” to this bit
11
0
0
-
10
0
0
-
“1” to“0”
9
0
0
-
corresponds to EP0.
0 :
1 :
<When RDYM bit is set to "0">
Invalid (Ignored when written)
<When RDYM bit is set to "1">
0 :
1 :
b6 corresponds to EP6, ---b1 corresponds to EP1 and b0
Read
Write
8
0
0
-
No occurrence of interrupt
Occurrence of interrupt
Clear interrupt clear
Invalid (Ignored when written)
7
0
0
-
6
0
0
-
Function
5
0
0
-
4
0
0
-
EPB_RDY
3
0
0
-
2
0
0
-
<S/W reset : H'0000>
<H/W reset :H'0000>
<Address : H’1A>
<USB bus reset : ->
1
0
0
-
R
0
b0
0
0
-
W
0