m66291 Renesas Electronics Corporation., m66291 Datasheet - Page 90

• Manufacturer Part Number: m66291
• Description: Assp Usb2.0 Device Controller
• Manufacturer: Renesas Electronics Corporation.

M 6 6 2 9 1 G P / H P
3.4 Control Transfer Overview
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(1) Setup stage
(2) Data stage
(3) Status stage
generating interrupt against the aforesaid stage transition.
error and continuous setup operations are shown in Figure 3.7 to Figure 3.12.
The control transfer is composed of three stages as follows:
The M66291 automatically controls the stages of the control transfers by the hardware and is capable of
The control transfers are executed by the endpoint 0.
The examples of control write transfer, control read transfer, control write no data transfer, control transfer
The transition to the setup stage occurs when the setup token is received.
The request data received at the setup stage (8 bytes) is automatically stored to four registers (Request, Value,
Index and Length) before the ACK response is executed.
For SET_ADDRESS request and SET_CONFIGURATION request, the M66291 can respond automatically to
the host. As for the other requests, execute data analysis (decoding) and processing by the software after the
setup stage complete interrupt has occurred.
When the setup token is received, the VALID bit is set to “1”, the EP0_PID and CCPL bits are changed as
shown below, then these bits are protected until the VALID bit is cleared:
The transition to the data stage occurs when the IN token/OUT token is received after the setup stage. In case
of the request with no data stage, the transition to the status stage executes by receiving the OUT token after
the setup stage.
The transition to the status stage occurs when IN token and OUT token are received after the data stage,
causing the control write/read transfer status transition interrupt to occur. In this case, setting the EP0_PID
bits to “01” and the CCPL bit to “1” enables to notify the normal completion to the host.
In the case of the request with no data stage, this interrupt works as the setup stage complete interrupt.
2 0 0 4 . 1 1 . 0 1
(1) Setup stage
(2) Data stage (some control transfers don't include)
(3) Status stage
• Control write transfer (OUT transaction)
• Control read transfer (IN transaction)
• EP0_PID bits
• CCPL bit
With the buffer set to receive ready state (buffer empty), the EP0_PID bits are set to “01” to make ACK
response to the host after receiving the data.
When the buffer is ready for data reading, the buffer ready interrupt occurs to enable reading of the
receive data by the EP0_FIFO Data Register.
With the buffer set to transmit ready state (buffer contains transmit data), the data is transmitted to
the host by setting the EP0_PID bits to “01”.
When the buffer is ready to accept new transmit data, the buffer ready interrupt occurs.
p a g e 9 0 o f 1 2 2
“00”
“0”
: NAK response (response at data stage)
: NAK response (response at status stage)