m66291 Renesas Electronics Corporation., m66291 Datasheet - Page 35

• Manufacturer Part Number: m66291
• Description: Assp Usb2.0 Device Controller
• Manufacturer: Renesas Electronics Corporation.

M 6 6 2 9 1 G P / H P
R e v 1 . 0 1
USB bus
Interrupt output
2 0 0 4 . 1 1 . 0 1
Note :
Figure 2.8 Examples of Buffer Ready Interrupt Occurrence Timing (OUT transfer)
Endpoint 1~6
The IVAL bit is located per endpoint. For details, refer to “3.2.4 IVAL Bit and EPB_RDY Bit”.
When set to OUT buffer (EPi_DIR bit = “0”)
When set to IN buffer (EPi_DIR bit = “1”)
The condition for this bit to be set to “1” is as follows:
The condition for this bit to be cleared to “0” differs according to the RDYM bit (Note):
The condition for this bit to be set to “1” is as follows:
The condition for this bit to be cleared to “0” differs according to the RDYM bits:
p a g e 3 5 o f 1 2 2
Note :
<The endpoint not specified by DMA_EP bits>
<The endpoint specified by DMA_EP bits with INTM bit set to “1”>
<The endpoint specified in DMA_EP bits with INTM bit set to “0”>
•
•
<The endpoint not specified by DMA_EP bits>
<The endpoint specified by DMA_EP bits with INTM bit set to “1”>
<The endpoint specified by DMA_EP bits with INTM bit set to “0”>
•
•
SYNC PID
•
•
RDYM bit = “0” : When the IVAL bit of the endpoint changes from “1” to “0”
RDYM bit = “1” : Writes “0” to this bit
•
•
RDYM bit = “0” : When the IVAL bit of the endpoint changes from “0” to “1”
RDYM bit = “1” : Writes “0” to this bit
When the IVAL bit of the endpoint changes from “0” to “1”
When the buffer data including the received short packet (including the zero-length
packet) are all read out
retained to “1”. Thus, it is necessary to write “1” to the BCLR bit and to clear the IVAL bit to
“0” when RDYM bit is set to “0”. Even when the RDYM bit is set to “1”, this bit can be cleared
by writing “0”. It is necessary to write “1” to the BCLR bit and to clear the IVAL bit.
When the IVAL bit of the endpoint changes from “1” to “0”
Or when EPi_DER bit is changed from “0” to “1”
This bit is not be set to “1”.
When the INTM bit at the endpoint specified by the DMA_EP bit is set to “0”, the IVAL bit is
OUT token
Addr Endp CRC EOP
SYNC PID
Occurrence of buffer ready interrupt
Data packet
Data CRC EOP
because the buffer could be read
SYNC PID
ACK packet
EOP