mic3003gfltr Micrel Semiconductor, mic3003gfltr Datasheet - Page 55

• Manufacturer Part Number: mic3003gfltr
• Description: Fom Management Ic With Internal Calibration
• Manufacturer: Micrel Semiconductor

Micrel, Inc.
July 2010
Default value
Serial address
Byte address
A write to OEMCFG0 will result in any A/D conversion in progress being aborted and the result discarded. The A/D will begin a
new conversion sequence once the write operation is complete.
All bits in OEMCFG0 are non-volatile except DFLT and RST. A valid OEM password is required for access to this register.
write only
D[7-3]
D[2:0]
D[2:0]
D[7]
D[6]
D[5]
D[4]
D[3]
D[7]
RST
Bit(s)
Bit(s)
RESETOUT
VAUX[2:0]
MODREF
QGPOS
DFLT
RST
OE
read/write
QGPOS
D[6]
Determines the state of QGPO in
GPO mode
Diode fault flag.
Output enable for SHDN, V MOD ,
and V BIAS .
Selects whether V MOD is
referenced to ground or V DD .
Selects the voltage reported in
VINh:VINl.
Function
Reserved
Function
Controls the reset output at pin 2
(QGPO) when Reset mode is
selected (OEMCFG3-7 set to 1)
read-only
DFLT
D[5]
OEM Configuration Register 0 (OEMCFG0)
0000 0000 b = 00 h
A6 h
00 = 00 h
reserved
D[4]
OE
Operation
0 = no action; 1 = reset
Issuing a software reset by setting RST high is equivalent to
a full power cycle of the MIC3003.
If OEMCFG3 bit 7 (QGPOM) is low, this bit determines
whether the QGPO output is high (undriven) or low (driven-
open-drain).
If QGPOM is high (Reset mode), this bit has no function
1 = diode fault; 0 = OK.
1 = enabled; 0 = hi-Z
1 = V DD ; 0 = GND
000 = V IN
001 = V DDA
010 = V BIAS
011 = V MOD
100 = APCDAC
101 = MODDAC
110 = FLTDAC
Operation
Read-only; these bits always return 00000.
By default, these three bits are 000, and the QGPO output
is undriven.
If RESET mode is selected in OEMCFG3:
When the three bits are written to 111, QGPO’s open-drain
output will be driven low for 125 μs (typical), after which
QGPO reenters the undriven state.
The RESETOUT field is cleared from 111 to 000 22.5 ms
(typical) after the de-assertion edge of QGPO. Other values
of this delay may be selected in the TRSTCLR[2:0] field in
OEMCFG2.
If Reset mode in OEMCFG3 is not selected, these three
bits have no function.
MODREF
55
reserved
D[3]
read/write
VAUX[2]
D[2]
[e-mail]
read/write
VAUX[1]
D[1]
or [phone]
read/write
M9999-072910-A
VAUX[0]
D[0]
MIC3003GFL