mic3003gfltr Micrel Semiconductor, mic3003gfltr Datasheet - Page 57

• Manufacturer Part Number: mic3003gfltr
• Description: Fom Management Ic With Internal Calibration
• Manufacturer: Micrel Semiconductor

Micrel, Inc.
July 2010
Default value
Serial address
Byte address
Caution: Changes to SMBADR take effect immediately. Any accesses following a write to SMBADR must be to the newly
programmed serial bus address.
A valid OEM password is required for access to this register. This register is non-volatile and will be maintained through power
and reset cycles.
D[7:4]
D[3:0]
SMBADR[3]
read/write
D[7]
Bit(s)
SMBADR[3:0]
TRSTCLR[2:0]
SMBADR[2]
read/write
D[6]
Function
Most significant four bits of the
serial bus device address
Set the delay between QGPO and
the clearing of RESETOUT
SMBADR[1]
read/write
D[5]
OEM Configuration Register 2 (OEMCFG2)
1010 0010 b = xx h (device address = 1010 xxxx b )
This value is the basis for using A0 h , A2 h , A4 h , and A6 h as the names of
the different device address spaces of the MIC3003.
A6 h
2 = 02 h
SMBADR[0]
read/write
D[4]
read/write
57
Operation
Writes take effect immediately.
These three bits set the delay between the de-assertion
edge of the QGPO output in Reset mode and the
subsequent clearing of the three RESETOUT bits in the
RESETOUT Register:
000: Zero delay
001: 17.5 ms typical
010: 22.5 ms typical (default)
011: 27.0 ms typical
100: 45 ms typical
Minimum and maximum values may be found by adding
tolerances of -10% and +10% to the above values.
If Reset mode is not selected, these bits have no function.
D[3]
TRSTCLR[2]
read/write
D[2]
[e-mail]
TRSTCLR[1]
read/write
D[1]
TRSTCLR[0]
or [phone]
read/write
M9999-072910-A
MIC3003GFL
D[0]