ptn3500dh NXP Semiconductors, ptn3500dh Datasheet - Page 10

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ptn3500dh

Manufacturer Part Number
ptn3500dh
Description
Maintenance And Control Device
Manufacturer
NXP Semiconductors
Datasheet
1. All the timing values are valid within the operating supply voltage and ambient temperature range and refer to V
Philips Semiconductors
I
NOTE:
2001 Jan 17
2
I
f
t
t
t
t
t
t
t
t
t
t
2
SCL
SW
BUF
SU;STA
HD;STA
r
f
SU;DAT
HD;DAT
VD;DAT
SU;STO
C-BUS TIMING CHARACTERISTICS
SYMBOL
Maintenance and control device
C-bus timing (see Figure 17; Note 1)
voltage swing of V
handbook, full pagewidth
PROTOCOL
SDA
SCL
SCL clock frequency
tolerable spike width on bus
bus free time
START condition set–up time
START condition hold time
SCL and SDA rise time
SCL and SDA fall time
data set–up time
data hold time
SCL LOW to data out valid
STOP condition set–up time
SS
t
to V
SU;STA
t
BUF
CONDITION
DD
START
.
(S)
t HD;STA
PARAMETER
r t
BIT 7
MSB
(A7)
t
t
SU;DAT
f
1 / f SCL
Figure 17.
BIT 6
(A6)
10
t
HD;DAT
MIN.
250
1.3
0.6
0.6
0.6
0
(R/W)
BIT 0
LSB
t
VD;DAT
ACKNOWLEDGE
TYP.
(A)
MBD820
IL
and V
CONDITION
MAX.
400
0.3
0.3
1.0
50
STOP
(P)
IH
t SU;STO
Product specification
PTN3500
with an input
SW00561
UNIT
kHz
ns
ns
ns
s
s
s
s
s
s
s

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