z87200 ZiLOG Semiconductor, z87200 Datasheet - Page 26

• Manufacturer Part Number: z87200
• Description: Spread-spectrum Transceiver
• Manufacturer: ZiLOG Semiconductor

FUNCTIONAL BLOCKS (Continued)
Z87200
Spread-Spectrum Transceiver
TXMCHP (Pin 19)
Transmit Manual Chip Pulse. TXMCHP enables the user
to provide the PN chip rate clock pulses from an external
source. This feature is useful in cases where a specific
chip rate is required that cannot be derived by the internal
clock generator which generates clocks of integer sub-
multiples of TXIFCLK. The signal is internally synchro-
nized to TXIFCLK to avoid intrinsic race or hazard timing
conditions.
When bit 2 of address 40
TXMCHP will generate the chip clock to the differential en-
coder and the following circuitry (Acquisition/Preamble
and Data Symbol PN spreaders, etc.). The rising edge of
TXMCHP is synchronized internally so that, on the third
rising edge of TXIFCLK following the rising edge of TXM-
CHP, the PN code combined with the differentially encod-
ed signal will change, generating the next chip.
TXIFCLK (Pin 14)
Transmitter I.F. Clock. TXIFCLK is the master clock of
the transmitter. All transmitter clocks, internal or external,
are generated or synchronized internally to the rising edge
of TXIFCLK. The rate of TXIFCLK must be at least twice
the transmit PN chip rate. It may be convenient to use the
same external signal for both TXIFCLK and RXIFCLK, in
which case the frequency of TXIFCLK will be at least four
times the PN chip rate as required for RXIFCLK. Moreover,
if the Z87200’s on-chip BPSK/QPSK Modulator is to be
used, TXIFCLK and RXIFCLK must be identical and
should not exceed 20 MHz.
MFLD (Pin 85)
Manual Frequency Load. MFLD is used to load a fre-
quency control value into the NCO. The NCO may be load-
ed in various ways, but MFLD provides a synchronized ex-
ternal method of updating the NCO, while the other
methods involve setting bit 0 of address 00H or using the
programmable loop filter timing circuitry. MFLD is internal-
ly synchronized to RXIFCLK to avoid internal race or haz-
ard timing conditions.
The MFLD input and bit 0 of address 00H are logically
ORed together so that, when either one is held low, a rising
edge on the other triggers the frequency load function
manually. The rising edge of MFLD is synchronized inter-
nally so that, on the sixth following rising edge of RXIF-
CLK, the frequency control word is completely registered
into the NCO accumulator. The frequency load command
must not be repeated until the six RXIFCLK cycle delay is
completed.
4-24
H
is set high, a rising edge on
PS010202-0601
/WR (Pin 28)
Write Bar. /WR is used to latch user-configurable informa-
tion into the control registers. It is important to note that the
control registers are transparent latches while /WR is set
low. The information will be latched when /WR returns
high. DATA
set low in order to avoid undesirable effects.
DATA
Data Bus. DATA
bus that provides access to all internal control register in-
puts for programming. DATA
the ADDR
trol registers.
ADDR
Address Bus. ADDR
the control register location into which the information pro-
vided on the DATA
in conjunction with /WR and DATA
tion into the registers.
/CSEL (Pin 29)
Chip Select Bar. /CSEL is provided to enable or disable
the microprocessor operation of the Z87200. When /CSEL
is set high, the ADDR
have no effect on the device. When /CSEL is set low, the
device is in its normal mode of operation and ADDR
/WR are active.
/OEN (Pin 49)
Output Enable Bar. /OEN is provided to enable or disable
the RXTEST
RXTEST
be connected to other busses, such as DATA
/OEN is set low, the RXTEST
the RXTEST function selected to be accessed.
/RESET (Pin 16)
Reset Bar. /RESET is the master reset of the Z87200,
clearing the control registers as well as the contents within
the receiver, transmitter, and NCO data paths when it is
set low. Setting /RESET high enables operation of the cir-
cuitry.
7-0
6-0
7-0
(Pins 20-27)
(Pins 32-38)
6-0
7-0
bus will have a high impedance, allowing it to
7-0
and /WR signals to set the values of the con-
and ADDR
output bus. When /OEN is set high, the
7-0
7-0
is an 8-bit microprocessor interface
6-0
bus will be written. ADDR
6-0
is a 7-bit address bus that selects
6-0
and /WR become disabled and
should be stable while /WR is
7-0
7-0
is used in conjunction with
bus will be active, allowing
7-0
to write the informa-
6-0
7-0
. When
is used
6-0
Zilog
and