sta013b STMicroelectronics, sta013b Datasheet - Page 8

• Manufacturer Part Number: sta013b
• Description: Mpeg 2.5 Layer Iii Audio Decoder
• Manufacturer: STMicroelectronics

STA013 - STA013B - STA013T
Figure 7. PLL and Clocks Generation System
2.4 - PCM Output Interface
The decoded audio data are output in serial PCM
format. The interface consists of the following sig-
nals:
SDO
SCKT
LRCLK
The output samples precision is selectable from
Figure 8. PCM Output Formats
Table 1: MPEG Sampling Rates (KHz)
8/38
LRCKT
SDO
SDO
SDO
SDO
LRCKT
SDO
SDO
PCM Serial Clock Output
Left/Right Channel Selection Clock
PCM Serial Data Output
MPEG 1
44.1
48
32
XTI
0
M
S
M
S
L
S
32 SCLK Cycles
16 SCLK Cycles
MSB
M
S
0
L
S
M
S
M
S
L
S
Update FRAC
FRAC
0
N
0
L
S
L
S
M
S
L
S
0
M
S
M
S
MSB
L
S
32 SCLK Cycles
16 SCLK Cycles
M
S
0
Switching
Circuit
L
S
M
S
M
S
L
S
M
0
0
PFD
L
S
L
S
L
S
M
S
MPEG 2
0
M
S
M
S
L
S
32 SCLK Cycles
22.05
16 SCLK Cycles
MSB
M
S
0
24
16
L
S
16 to 24 bits/word, by setting the output precision
with PCMCONF (16, 18, 20 and 24 bits mode)
register. Data can be output either with the most
significant bit first (MS) or least significant bit first
(LS), selected by writing into a flag of the
PCMCONF register.
Figure 8 gives a description of the several
STA013 PCM Output Formats.
The sample rates set decoded by STA013 is de-
scribed in Table 1.
VCO
M
S
M
S
CP
L
S
Disable PLL
0
0
XTI2OCLK
XTI2DSPCLK
L
S
M
S
L
S
L
S
0
M
S
M
S
L
S
32 SCLK Cycles
MSB
16 SCLK Cycles
M
S
0
L
S
M
S
M
S
L
S
X
S
0
0
C
L
S
M
S
L
S
L
S
32 SCLK Cycles
PCM_FORMAT = 1
PCM_DIFF = 1
PCM_FORMAT = 0
PCM_DIFF = 0
PCM_FORMAT = 0
PCM_DIFF = 1
PCM_FORMAT = 1
PCM_DIFF = 1
16 SCLK Cycles
PCM_ORD = 0
PCM_PREC is 16 bit mode
PCM_ORD = 1
PCM_PREC is 16 bit mode
R
C
OCLK
DCLK
MPEG 2.5
11.025
12
8