sta335bwqs STMicroelectronics, sta335bwqs Datasheet - Page 33

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sta335bwqs

Manufacturer Part Number
sta335bwqs
Description
2.1-channel High-efficiency Digital Audio System With Qsound Qhd?
Manufacturer
STMicroelectronics
Datasheet
STA335BWQS
7.3
7.3.1
7.3.2
Configuration register C (addr 0x02)
DDX
Table 23.
The DDX power output mode selects how the DDX output timing is configured.
Different power devices use different output modes.
Table 24.
DDX
Table 25.
Table 26.
Table 6:
Bit
Bit
0
1
2
3
4
5
OCRB
D7
1
®
®
CSZ[3:0]
OM[1,0]
0000
0001
1111
power output mode
compensating pulse size register
00
01
10
11
R/W
R/W
RW
RW
RW
RW
RW
RW
OM
Output modes
CSZ
Compensating pulse size
Reserved
D6
0
RST
RST
1
1
1
0
1
0
0 ns (0 ticks) compensating pulse size
20 ns (1 tick) clock period compensating pulse size
300 ns (15 ticks) clock period compensating pulse size
Drop compensation
Discrete output stage - tapered compensation
Full power mode
Variable drop compensation (CSZx bits)
CSZ3
D5
0
Name
Name
CSZ0
CSZ1
CSZ2
CSZ3
OM0
OM1
CSZ2
D4
1
Compensating Pulse Size
Selects configuration of DDX output.
When OM[1,0] = 11, this register determines the
size of the DDX compensating pulse from 0 clock
ticks to 15 clock periods.
Output stage - mode
CSZ1
D3
0
CSZ0
Description
Description
D2
1
Register description
OM1
D1
1
OM0
D0
1
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