sta381bw STMicroelectronics, sta381bw Datasheet - Page 128

• Manufacturer Part Number: sta381bw
• Description: Sound Terminal 2.1-channel High-efficiency Digital Audio System
• Manufacturer: STMicroelectronics

Register description: Sound Terminal compatibility
7.11
7.11.1
7.11.2
7.11.3
7.11.4
128/168
Dynamic control registers (addr 0x12 - 0x15)
Limiter 1 attack/release rate
Limiter 1 attack/release threshold
Limiter 2 attack/release rate
Limiter 2 attack/release threshold
The STA381BW includes two independent limiter blocks (not to be mistaken with the
STCompressor
purpose of the limiters is to automatically reduce the dynamic range of a recording to
prevent the outputs from clipping in anticlipping mode or to actively reduce the dynamic
range for a better listening environment such as a nighttime listening mode which is often
needed for DVDs. The two modes are selected via the DRC bit in
(addr 0x04) on page
meaning that the channel will clip when 0 dBfs is exceeded. Each limiter looks at the present
value of each channel that is mapped to it, selects the maximum absolute value of all these
channels, performs the limiting algorithm on that value, and then, if needed, adjusts the gain
of the mapped channels in unison.
The limiter attack thresholds are determined by the LxAT registers if the EATHx[7] bits are
set to 0, else the thresholds are determined by EATHx[6:0]. It is recommended in
anticlipping mode to set this to 0 dBfs, which corresponds to the maximum unclipped output
power of an FFX amplifier. Since gain can be added digitally within the STA381BW, it is
possible to exceed 0 dBfs or any other LxAT setting. When this occurs, the limiter, when
active, automatically starts reducing the gain. The rate at which the gain is reduced when
the attack threshold is exceeded is dependent upon the attack rate register setting for that
limiter. Gain reduction occurs on a peak-detect algorithm. Setting the EATHx[7] bits to 1
selects the anticlipping mode.
The limiter release thresholds are determined by the LxRT registers if the ERTHx[7] bits are
set to 0, else the thresholds are determined by ERTHx[6:0]. Settings the ERTHx[7] bits to 1
L1AT3
L2AT3
L1A3
L2A3
D7
D7
D7
D7
0
0
0
0
L1AT2
L2AT2
TM
L1A2
L2A2
D6
D6
D6
D6
1
1
1
1
, for further details about this feature please refer to
112. Each channel can be mapped to either limiter or not mapped,
L1AT1
L2AT1
L1A1
L2A1
D5
D5
D5
D5
1
1
1
1
Doc ID 018835 Rev 2
L1AT0
L2AT0
L1A0
L2A0
D4
D4
D4
D4
0
0
0
0
L1RT3
L2RT3
L1R3
L2R3
D3
D3
D3
D3
1
1
1
1
L1RT2
L2RT2
L1R2
L2R2
D2
D2
D2
D2
0
0
0
0
Configuration register E
L1RT1
L2RT1
L1R1
L2R1
D1
D1
D1
D1
1
0
1
0
Section
STA381BW
4.2). The
L1RT0
L2RT0
L1R0
L2R0
D0
D0
D0
D0
0
1
0
1