saa6713ah NXP Semiconductors, saa6713ah Datasheet - Page 14

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saa6713ah

Manufacturer Part Number
saa6713ah
Description
Xga Analog Input Flat Panel Controller
Manufacturer
NXP Semiconductors
Datasheet

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7.1.2.4
When transmitting a series of data bytes, after a data byte
has been written or read, the subaddress for the following
byte is automatically updated to allow burst access. During
burst access a sequence of data bytes is written or read
without repeated device or subaddressing. In general, the
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subaddress as the succeeding byte’s subaddress.
Auto-incrementing is suppressed for several addresses
that provide access to the on-chip parameter RAM. In the
event of upscaler register USC_LUT_DATA (02H at
page 7) subsequent data is written to the same
subaddress and the scaling curve RAM address is
incremented instead.
For OSD registers OSDT_PROP2 to OSDT_PROP0,
OSDB_DEF and OSDP_DEF (0FH to 11H, 31H and 4CH
at page 8) and colour look-up table register
CL_VALUE_LO (03H at page 10) different subaddress
update modes are selectable and are described in the
respective subsection.
7.1.2.5
Parameters or read-out data words consisting of more
than 8 bits are mapped into the address space in the order
highest byte at the lowest address to lowest byte at the
highest address. Multiple byte configuration parameters
have to be written lowest address first and only become
effective, once the byte of the highest address was written.
Multiple byte read registers have to be read-out in the
same order.
2004 Apr 05
2
C-bus auto-increment feature uses the next higher
XGA analog input flat panel controller
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Multiple byte parameters
2
C-bus subaddress
14
7.1.2.6
Register IIC_TEST (02H at page 0) is a read and write
register that can be used to verify correct operations of the
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7.1.3
The global registers are listed in Table 6.
The page-mapped registers are listed for each register
page in Tables 7 to 17.
2
C-bus. Any programmed value can be read back.
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2
C-
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2
C-bus test register
BUS REGISTER LISTING
SAA6713AH
Product specification

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