qt60326 Quantum Research Group, qt60326 Datasheet - Page 12

• Manufacturer Part Number: qt60326
• Description: 32 & 48 Key Qmatrix Ics
• Manufacturer: Quantum Research Group

SPI communications operates in slave mode only, and obeys
DRDY control signaling. The clocking is as follows:
SPI mode requires 5 signals to operate:
MOSI - Master out / Slave in data pin; used as an input for data
MISO - Master in / Slave out data pin; used as an output for
SCK - SPI clock - input only clock from host. The host must shift
/SS - Slave select - input only; acts as a framing signal to the
DRDY - Data Ready - active-high - indicates to the host that the
The MISO pin on the QT floats in 3-state mode between bytes
when /SS is high. This facilitates multiple devices on one SPI
bus.
Null Bytes: When the QT responds to a command with one or
more response bytes, the host should issue a null commands
(0x00) to get the response bytes back. The host should not
send new commands until all the responses are accepted back
from the QT from the prior command via nulls.
)
(Data from Host)
(Data from QT)
from the host (master). This pin should be connected to the
MOSI (DO) pin of the host device.
data to the host. This pin should be connected to the M ISO
(DI) pin of the host. MISO floats when /SS is high to allow
multi-drop communications along with other slave parts.
out data on the falling SCK edge; the QT60xx6 clocks data in
on the rising edge. The QT60xx6 likewise shifts data out on
the falling edge of SCK back to the host so that the host can
shift the data in on the rising edge. Important: SCK must
idle high; it should never float.
sensor from the host. /SS must be low before and during
reception of data from the host. It must not go high again
until the SCK line has returned high; /SS must idle high. This
pin includes an internal pull-up resistor of 20K ~ 50K. When
/SS is high, MISO floats.
QT is ready to send or receive data. This pin idles high. This
pin includes an internal pull-up resistor of 20K ~ 50K. In SPI
mode this pin is an output only (i.e. open drain with internal
pull-up).
(from Host)
(from Host)
(from QT)
DRDY
MOSI
MISO
CLK
Clock idle:
Clock shift out edge:
Clock data in edge:
Max clock rate:
/SS
3-state
?
high via pullup-R
? 7
S2
7
Data shifts out of QT on falling edge
Data shifts in to QT on rising edge
S1
6
6
{Command byte}
S5: >20µs
5
5
4
4
3
3
Figure 3-3 SPI Slave-Only Mode Timing (Fosc = 16MHz)
2
2
High
Falling
Rising
4MHz
S1: P125ns
1
1
0
0
S6: P1µs
S3
3-state
S4
S2: >20ns
S5
S6
S7: P125ns
? 7
7
12
6
6
{optional 2nd command byte}
New commands attempted during intermediate byte transfers
are ignored.
Wake operation: The device can be put into sleep mode with a
serial command, 0x16 (page 16) and then be awakened later
with a 10µs minimum low level on the WS pin. With the /SS line
tied to WS, the host can simply toggle /SS low for 10µs
minimum to wake the part; the host should not send an actual
SPI byte to prevent the device from seeing a byte it cannot
properly interpret due to timing errors during wakeup.
The recommended method to reestablish communications after
Wake from Sleep is to send the QT device a 0x0F ('Get Last
Command' command) repeatedly until the correct response
comes back (the command's own compliment, i.e. 0xF0).
SPI Line Noise: In some designs it is necessary to run SPI
lines over ribbon cable across a lengthy distance on a PCB.
This can introduce ringing, ground bounce, and other noise
problems which can introduce false SPI clocking or false data.
Simple RC networks and slower data rates are helpful to
resolve these issues as shown in Figure 3-2.
CRC checks have also been added to critical commands in
order to detect transmission errors to a high level of certainty.
3.3 UART Communications
See also SR setup parameter, page 23.
UART mode is selected as soon as the QT receives any data
on the UART Rx pin. There is no other configuration required to
make the device operate in UART mode. Once UART is
selected after a power-up, the device cannot switch to SPI
mode unless the device is reset.
UART mode communications functions in the same basic way
as SPI communications. The Baud rate is adjusted by means of
setup parameter ‘SR’ (page 23). Once a new Baud rate has
been set, the device must be reset for the new rate to take
effect.
The major difference with SPI mode is that the UART mode is
asynchronous and so the host does not clock the QT. No
framing /SS or clock signal is required, simplifying the interface
greatly. Return data is sent from the QT back to the host when
the data is ready.
5
5
S3: P25ns
S7
4
4
3
3
2
2
S8
S8: P125ns
1
1
0
0
S9
S4: >20ns
S9: P250ns
QT60486-AS R8.01/0105
{null byte or next command to get QT response}
? 7
7
6
6
data response
5
5
4
4
3
3
2
2
1
1
0
0