qt60326 Quantum Research Group, qt60326 Datasheet - Page 23

• Manufacturer Part Number: qt60326
• Description: 32 & 48 Key Qmatrix Ics
• Manufacturer: Quantum Research Group

External fields can cause interference leading to false
detections or sensitivity shifts. Most fields come from AC
power sources. RFI noise sources are heavily suppressed
by the low impedance nature of the QT circuitry itself.
Noise such as from 50Hz or 60Hz fields becomes a problem
if it is uncorrelated with acquisition signal sampling;
uncorrelated noise can cause aliasing effects in the key
signals. To suppress this problem the WS input allows bursts
to synchronize to the noise source. This same input can also
be used to wake the part from a low-power Sleep state.
The noise sync operating mode is set by parameter MSYNC
in Setups.
The sync occurs only at the burst for the lowest numbered
enabled key in the matrix; the device waits for the sync
signal for up to 100ms after the end of a preceding full matrix
scan, then when a negative sync edge is received, the matrix
is scanned in its entirety again.
The sync signal drive should be a buffered logic signal, or
perhaps a diode-clamped signal, but never a raw AC signal
from the mains. The device will sync to the falling edge.
Since Noise sync is highly effective and inexpensive to
implement, it is strongly advised to take advantage of it
anywhere there is a possibility of encountering low frequency
(i.e. 50/60Hz) electric fields. Quantum’s QmBtn software can
show such noise effects on signals, and will hence assist in
determining the need to make use of this feature.
If the sync feature is enabled but no sync signal exists, the
sensor will continue to operate but with a delay of 100ms
from the end of one scan to the start of the next, and hence
will have a slow response time. A failed Sync signal (one
exceeding a 100ms period) will cause an error flag (see
commands 0x05, 0x06).
MSYNC Default value:
MSYNC Possible range:
5.13 Burst Spacing - BS
The interval of time from the start of one burst to the start of
the next is known as the burst spacing. This is an alterable
parameter which affects all keys. The burst spacing can be
viewed as a scheduled timeslot in which a burst occurs. This
approach results in an orderly and predictable sequencing of
key scanning with predictable response times.
Shorter spacings result in a faster response time to touch;
longer spacings permit higher burst lengths and longer
conversion times but slow down response time.
An automatic setting is also available that performs a ‘best
fit’ timeslot determination for each key’s acquisition burst.
The fit is determined on power-up each time and is fixed
thereafter until reset again.
See Table 5.4 (page 26) for possible values.
BS Default value:
BS Possible range:
5.14 Serial Rate - SR
The possible Baud rates are shown in Table 5.4. The rate
chosen by this parameter only affects UART mode. SPI
mode is slave-only and can clock at any rate from DC up to
4Mhz.
)
0 (Automatic)
0..11 (Auto, 500µs .. 3ms)
0 (Off)
0, 1 (Off, On)
23
The Baud rate can be adjusted to one of 5 values from 9600
to 115.2K baud.
SR Default value:
5.15 Lower Signal Limit - LSL
This Setup determines the lowest acceptable value of signal
level for all keys. If any key’s reference level falls below this
value, the device declares an error condition in the key
status bits (Sections 4.5, 4.6, 4.8, 4.11).
Testing is required to ensure that there are adequate
margins in this determination. Key size, shape, panel
material, burst length, and dwell time all factor into the
detected signal levels.
This parameter occupies 2 bytes of the setups table. The low
order byte should be sent first.
LSL Default value:
LSL Possible range:
5.16 LED / Alert Output - LED
Refer also to Table 5.2 page 25 for details.
Pin 40 is designed to drive a low-current LED or to be used
as a status and error signaling mechanism for the host
controller, primarily for FMEA purposes.
One use for this pin is to alert the host that there is key
activity, in order to limit the amount of communication
between the device and the host. The LED pin should ideally
be connected to an interrupt pin on the host that can detect
an edge, following which the host can proceed to poll the
device for key activations.
Note that LED polarity can be reversed in the setups byte.
Table 5.2, on page 25 shows the possible internal conditions
that can cause the LED pin to go active. The various items in
the table are logical-OR’d together.
The LED pin can even be used as a watchdog for the host,
to reset it should the host fail to send regular transmissions
to the QT (bit 0 of LED byte). The comms timeout required to
generate the ‘reset’ signal is about 2 seconds of inactivity. If
this feature is enabled, it does not become effective until the
first command is received from the host; therefore, it is
assumed that there is at least some initial host activity for
this feature to work.
Note that the LED state will be preserved during sleep.
LED Default value:
5.17 Host CRC - HCRC
The setups block terminates with a 16-bit CRC, HCRC, of
the entire block. The formulae for calculating this CRC and
the 8-bit CRC also used in the device are shown in Section
7. The low order byte should be sent first.
(see Table 5.2, page 25 for details)
0 (9600 Baud)
100 (recommended value)
0..2047
QT60486-AS R8.01/0105
0x6c