aduc7033bstz-8l-rl Analog Devices, Inc., aduc7033bstz-8l-rl Datasheet - Page 13
aduc7033bstz-8l-rl
Manufacturer Part Number
aduc7033bstz-8l-rl
Description
Integrated Precision Battery Sensor For Automotive
Manufacturer
Analog Devices, Inc.
Datasheet
1.ADUC7033BSTZ-8L-RL.pdf
(136 pages)
- Current page: 13 of 136
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Table 5. SPI Slave Mode Timing (PHASE Mode = 0)
Parameter
t
t
t
t
t
t
t
t
t
t
t
t
1
2
SL
SH
DAV
DSU
DHD
DF
DR
SR
SF
DOCS
SFS
t
t
SS
HCLK
UCLK
depends on the clock divider or CD bits in PLLCON MMR. t
= 48.8 ns. It corresponds to the 20.48 MHz internal clock from the PLL before the clock divider.
(POLARITY = 0)
(POLARITY = 1)
Description
SS to SCLK edge
SCLK low pulse width
SCLK high pulse width
Data output valid after SCLK edge
Data input setup time before SCLK edge
Data input hold time after SCLK edge
Data output fall time
Data output rise time
SCLK rise time
SCLK fall time
Data output valid after SS edge
SS high after SCLK edge
SCLK
SCLK
MISO
MOSI
SS
t
DOCS
t
CS
1
t
1
DSU
MSB IN
MSB
t
DHD
t
SH
2
Figure 5. SPI Slave Mode Timing (PHASE Mode = 0)
2
t
DF
HCLK
2
t
DAV
= t
UCLK
t
SL
Rev. 0 | Page 13 of 136
/2
t
CD
DR
.
BITS [6:1]
BITS [6:1]
Min
0
4 × t
UCLK
Typ
½ t
(SPIDIV + 1) × t
(SPIDIV + 1) × t
3.5
3.5
3.5
3.5
½ t
SL
SL
LSB IN
t
SR
LSB
HCLK
HCLK
t
SF
Max
(3 × t
(3 × t
t
SFS
UCLK
UCLK
) + (2 × t
) + (2 × t
HCLK
HCLK
ADuC7033
)
)
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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