aduc7033bstz-8l-rl Analog Devices, Inc., aduc7033bstz-8l-rl Datasheet - Page 25

• Manufacturer Part Number: aduc7033bstz-8l-rl
• Description: Integrated Precision Battery Sensor For Automotive
• Manufacturer: Analog Devices, Inc.

RESET
There are four kinds of reset: external reset, power-on-reset,
watchdog reset, and software reset. The RSTSTA register
indicates the source of the last reset and can also be written by
user code to initiate a software reset event. The bits in this
register can be cleared to 0 by writing to the RSTCLR MMR at
0xFFFF0234. The bit designations in RSTCLR mirror those of
RSTSTA. These registers can be used during a reset exception
service routine to identify the source of the reset. The implica-
tions of all four kinds of reset event are tabulated in Table 12.
RSTSTA Register
Name:
Address:
Default Value:
Access:
Function:
Table 12. Device Reset Implications
Reset
Source
POR
Watchdog
Software
External Pin
1
2
RAM is not valid in the case of a reset following LIN download.
The impact on SRAM is dependent on the HVSTA[6] contents if LVF is enabled. When LVF is enabled using HVCFG0[2], SRAM has not been corrupted by the POR reset
mechanism if the LVF Status Bit HVSTA[6] is 1. See the Low Voltage Flag (LVF) section for more information.
Reset
External Pins
to Default
State
Yes
Yes
Yes
Yes
RSTSTA
0xFFFF0230
Depends on type of reset
Read/write access
This 8-bit register indicates the source of the
last reset event and can also be written by
user code to initiate a software reset.
Kernel
Executed
Yes
Yes
Yes
Yes
Reset All
External MMRs
(Excluding
RSTSTA)
Yes
Yes
Yes
Yes
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Reset All HV
Indirect
Registers
Yes
Yes
Yes
Yes
Impact
RSTCLR Register
Name:
Address:
Access:
Function:
Table 11. RSTSTA/RSTCLR MMR Bit Designations
Bit
7 to 4
3
2
1
0
1
clear this bit generates a software reset.
If the software reset bit in RSTSTA is set, any write to RSTCLR that does not
Peripherals
Reset
Yes
Yes
Yes
Yes
RSTCLR
0xFFFF0234
Write only
This 8-bit write only register clears the
corresponding bit in RSTSTA.
Description
Not Used. These bits are not used and always
read as 0.
External Reset.
Software Reset.
Watchdog Timeout.
Power-On Reset.
Automatically set to 1 when an external reset occurs.
Cleared by setting the corresponding bit in
RSTCLR.
Set to 1 by user code to generate a soft-
ware reset.
Cleared by setting the corresponding bit in
RSTCLR.
Automatically set to 1 when a watchdog timeout
occurs.
Cleared by setting the corresponding bit in
RSTCLR.
Automatically set when a power-on-reset occurs.
Cleared by setting the corresponding bit in
RSTCLR.
1
Watchdog
Timer Reset
Yes
No
No
No
SRAM
Valid
Yes/No
Yes
Yes
Yes
1
2
ADuC7033
RSTSTA
(Status After
Reset Event)
RSTSTA[0] = 1
RSTSTA[1] = 1
RSTSTA[2] = 1
RSTSTA[3] = 1