aduc7033bstz-8l-rl Analog Devices, Inc., aduc7033bstz-8l-rl Datasheet - Page 17
aduc7033bstz-8l-rl
Manufacturer Part Number
aduc7033bstz-8l-rl
Description
Integrated Precision Battery Sensor For Automotive
Manufacturer
Analog Devices, Inc.
Datasheet
1.ADUC7033BSTZ-8L-RL.pdf
(136 pages)
- Current page: 17 of 136
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Pin No.
7
8, 34, 35
9, 16, 17,
23, 25, 26,
32, 38 to
40, 43, 45
10
11
12
13
14
15
18
19
20
21, 22
24
27
28
29
30
Mnemonic
TDI
DGND
NC
TDO
NTRST
TMS
VBAT
VREF
GND_SW
VTEMP
IIN+
IIN−
AGND
REG_AVDD
GPIO_0/IRQ0/SS
GPIO_1/SCLK
GPIO_2/MIS0
GPIO_3/MOSI
Type
I
S
O
I
I
I
I
I
I
I
I
S
S
I/O
I/O
I/O
I/O
1
Description
JTAG Test Data Input. This data input pin is one of the standard 5-pin JTAG debug ports on the
part. TDI is an input pin only and has an internal weak pull-up resistor. This pin remains
unconnected when not in use.
Ground Reference for On-Chip Digital Circuits.
No Connect. These pins are not internally connected, but are reserved for possible future use.
Therefore, do not externally connect these pins. These pins can be grounded, if required.
JTAG Test Data Output. This data output pin is one of the standard 5-pin JTAG debug ports on
the part. TDO is an output pin only. At power-on, this output is disabled and pulled high via an
internal weak pull-up resistor. This pin remains unconnected when not in use.
JTAG Test Reset. This reset input pin is one of the standard 5-pin JTAG debug ports on the part.
NTRST is an input pin only and has an internal, weak, pull-down resistor. This pin remains
unconnected when not in use. NTRST is also monitored by the on-chip kernel to enable LIN
boot load mode.
JTAG Test Mode Select. This mode select input pin is one of the standard 5-pin JTAG debug
ports on the part. TMS is an input pin only and has an internal weak pull-up resistor. This pin
remains unconnected when not in use.
Battery Voltage Input to Resistor Divider.
External Reference Input Terminal. When this input is not used, connect it directly to the AGND
system ground. It can also remain unconnected.
Switch to Internal Analog Ground Reference. This pin is the negative input for the external
temperature channel and external reference. When this input is not used, connect it directly to
the AGND system ground.
External Pin for NTC/PTC Temperature Measurement.
Positive Differential Input for Current Channel.
Negative Differential Input for Current Channel.
Ground Reference for On-Chip Precision Analog Circuits.
Nominal 2.6 V Output from On-Chip Regulator.
General-Purpose Digital Input/Output 0, External Interrupt Request 0, or SPI Interface. This is a
multifunction pin. By default and after power-on-reset, this pin is configured as an input. The
pin has an internal weak pull-up resistor. This pin remains unconnected when not in use. This
multifunction pin can be configured in one of three states, namely
General-Purpose Digital Input/Output 1, SPI Interface. This is a multifunction pin. By default
and after power-on-reset, this pin is configured as an input. The pin has an internal weak pull-
up resistor. This pin remains unconnected when not in use. This multifunction pin can be
configured in one of two states, namely
General-Purpose Digital Input/Output 2, SPI Interface. This is a multifunction pin. By default
and after power-on-reset, this pin is configured as an input. The pin has an internal weak pull-
up resistor. This pin remains unconnected when not in use. This multifunction pin can be
configured in one of two states, namely
General-Purpose Digital Input/Output 3, SPI Interface. This is a multifunction pin. By default
and after power-on reset, this pin is configured as an input. The pin has an internal weak pull-
up resistor. This pin remains unconnected when not in use. This multifunction pin can be
configured in one of two states, namely
General-Purpose Digital I/O 0.
External Interrupt Request 0, active high.
SPI interface, slave select input.
General-Purpose Digital I/O 1.
SPI interface, serial clock input.
General-Purpose Digital I/O 2.
SPI interface, master input/slave output pin.
General-Purpose Digital I/O 3.
SPI interface, master output/slave input pin.
Rev. 0 | Page 17 of 136
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