lm25066apsqx National Semiconductor Corporation, lm25066apsqx Datasheet - Page 22

• Manufacturer Part Number: lm25066apsqx
• Description: Lm25066a System Power Management And Protection Ic With Pmbus
• Manufacturer: National Semiconductor Corporation

www.national.com
TIMER CAPACITOR, C
The TIMER pin capacitor (C
time delay, fault timeout period, and the restart timing of the
LM25066A.
A) Insertion Delay - Upon applying the system voltage
(V
during the insertion time (t
transients at V
to a circuit card plug-in is unique, the worst case settling time
must be determined for each application. The insertion time
starts when VIN reaches the POR threshold, at which time the
internal 5.5 µA current source charges C
The required capacitor value is calculated from:
For example, if the desired insertion delay is 250 ms, C
culates to 0.8 µF. At the end of the insertion delay, C
quickly discharged by a 1.9 mA current sink.
B) Fault Timeout Period - During in-rush current limiting or
upon detection of a fault condition where the current limit and/
or power limit circuits regulate the current through Q
timer current source (90 µA) is switched on to charge C
Fault Timeout Period is the time required for the TIMER pin
voltage to reach 1.7V, at which time Q
required capacitor value for the desired Fault Timeout Period
t
For example, if the desired Fault Timeout Period is 15 ms,
C
sink at the end of the Fault Timeout Period. After the Fault
Timeout Period, if retry is disabled, the LM25066A latches the
GATE pin low until a power up sequence is initiated by exter-
nal circuitry. When the Fault Timeout Period of the LM25066A
FAULT
T
SYS
calculates to 0.8 µF. C
) to the circuit, the external MOSFET (Q
is calculated from:
SYS
to settle. Since each backplane’s response
T
T
is discharged by the 2.8 µA current
1
T
in
) sets the timing for the insertion
Figure
2) to allow ringing and
1
is switched off. The
FIGURE 9. MOSFET Power Up Waveforms
T
from 0V to 1.7V.
1
) is held off
1
, the fault
T
T
. The
cal-
T
(7)
(8)
is
22
expires, a restart sequence starts as described below
(Restart Timing). During consecutive cycles of the restart se-
quence, the fault timeout period is shorter than the initial fault
timeout period described above by approximately 20% since
the voltage at the TIMER pin starts ramping up from 0.3V
rather than ground.
Since the LM25066A normally operates in power limit and/or
current limit during a power up sequence, the Fault Timeout
Period MUST be longer than the time required for the output
voltage to reach its final value. See the Turn-On Time section.
C) Restart Timing For the LM25066A, after the Fault Timeout
Period described above, C
rent sink to 1V. The TIMER pin then cycles through seven
additional charge/discharge cycles between 1V and 1.7V as
shown in
voltage reaches 0.3V during the final high-to-low ramp. The
restart time, after the Fault Timeout Period, is equal to:
For example, if C
of the restart time, Q
the fault timeout and restart sequence repeats. The on-time
duty cycle of Q1 is approximately 0.67% in this mode.
UVLO, OVLO
By programming the UVLO and OVLO thresholds the
LM25066A enables the series pass device (Q
put supply voltage (V
range. If V
LO threshold, Q
Hysteresis is provided for each threshold.
Option A: The configuration shown in
three resistors (R1-R3) to set the thresholds.
Figure
SYS
is below the UVLO threshold, or above the OV-
1
4. The restart time ends when the TIMER pin
T
is switched off, denying power to the load.
= 0.8 µF, t
1
is switched on. If the fault is still present,
SYS
= C
) is within the desired operational
T
T
is discharged by the 2.8 µA cur-
RESTART
x 2.3 x 10
= 2 seconds. At the end
6
Figure 10
30146025
1
) when the in-
requires
(10)
(9)