ip4778cz38/v NXP Semiconductors, ip4778cz38/v Datasheet - Page 14

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ip4778cz38/v

Manufacturer Part Number
ip4778cz38/v
Description
Hdmi Esd Protection, Ddc Buffering And Hot Plug Control
Manufacturer
NXP Semiconductors
Datasheet
NXP Semiconductors
IP4778CZ38_1
Objective data sheet
Fig 8.
(1) Dotted line indicates effect without slew rate accelerator.
DDC output waveform
10.3 Hot plug driver circuit
10.4 CEC
The IP4778CZ38 includes a hot plug driver circuit that simplifies the hot plug application.
The circuit can be connected directly to GPIO pins.
The hot plug control input is actively pulled LOW to ensure that at system standby or
startup, the hot plug signal is HIGH even if a GPIO pin is in a 3-state condition. The
switching of the pull-up and the pull-down resistor provides a guaranteed hot plug input
resistance (R
For correct CEC handling, it is essential that the hot plug signal is at HIGH-level in
Standby mode. The HDMI source requires a hot plug signal so that it can read out the
EDID information to initiate a proper startup CEC sequence.
The CEC signal can generate distortions caused by signal ringing in a 1 kHz domain. The
CEC slew rate limiter ensures that a signal does not ring independently of the CEC slave
that is releasing the signal.
A MOSFET transistor implements the backdrive protection which blocks signals during a
power-down state.
The slew rate of the CEC bus is controlled by a slew rate that is defined independently of
the load (ohmic and capacitive) at the CEC bus.
Fig 9.
0.3V
CC(5V0)
Hot plug driver circuit
HOT_PLUG_DET_OUT
i
) to comply with the HDMI specification.
Rev. 01 — 10 April 2008
(1)
TMDS_BIAS
HDMI ESD protection, DDC buffering and hot plug control
V
CC(5V0)
1 k
50 A
001aag043
10 A
ENABLE
HOT_PLUG_DET_IN
IP4778CZ38
(1)
001aag042
© NXP B.V. 2008. All rights reserved.
5.0 V
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