pdi1394p23 NXP Semiconductors, pdi1394p23 Datasheet - Page 29

• Manufacturer Part Number: pdi1394p23
• Description: 2-port/1-port 400 Mbps Physical Layer Interface
• Manufacturer: NXP Semiconductors

Philips Semiconductors
subsequently interrupts the status transfer. Register contents are
considered to have been successfully transmitted only when all
8 bits of the register have been sent. A status transfer is retried after
being interrupted only if any status flags remain to be sent, or if a
register transfer has not yet completed.
The definition of the bits in the status transfer is shown in Table 18,
and the timing is shown in Figure 15.
The sequence of events for a status transfer is as follows:
Table 18. Status Bits
18.3 Receive
Whenever the PHY detects the data-prefix state on the serial bus, it
initiates a receive operation by asserting Receive on the CTL terminals
and a logic 1 on each of the D terminals (“data-on” indication). The
PHY indicates the start of a packet by placing the speed code
(encoded as shown in Table 19) on the D terminals, followed by
packet data. The PHY holds the CTL terminals in the Receive state
until the last symbol of the packet has been transferred. The PHY
indicates the end of packet data by asserting Idle on the CTL
terminals. All received packets are transferred to the LLC. Note that
the speed code is part of the PHY-LLC protocol and is not included in
the calculation of CRC or any other data protection mechanisms.
2001 Sep 06
asserting status on the CTL lines along with the status data on the
BIT(S)
Status transfer initiated. the PHY indicates a status transfer by
8–15
2-port/1-port 400 Mbps physical layer interface
4–7
0
1
2
3
Arbitration Reset Gap
Subaction gap
Bus reset
Interrupt
Address
Data
NAME
CTL0, CTL1
SYSCLK
D0, D1
Indicates that the PHY has detected that the bus has been idle for a subaction gap time (as defined in the
Indicates that the PHY has detected that the bus has been idle for an arbitration reset gap time (as
defined in the IEEE 1394–1995 standard). This bit is used by the LLC in the busy/retry state machine.
IEEE 1394–1995 standard). This bit is used by the LLC to detect the completion of an isochronous cycle.
Indicates that the PHY has entered the bus reset state.
Indicates that a PHY interrupt event has occurred. An interrupt event may be a configuration time-out, a
cable-power voltage falling too low, a state time-out, or a port status change.
This field holds the address of the PHY register whose contents are being transferred to the LLC.
This field holds the register contents.
00
00
Figure 15. Status Transfer Timing
(a)
S[0:1]
01
29
the data-prefix state on the serial bus followed by the data-end state,
Table 19. Speed Code for the Receiver
It is possible for the PHY to receive a null packet, which consists of
D0–D7
0000 0000
0100 0000
0101 0000
1111 1111
D0 and D1 lines (only 2 bits of status are transferred per cycle).
Normally (unless interrupted by a receive operation), a status
transfer will be either 2 or 8 cycles long. A 2-cycle (4 bit) transfer
occurs when only status information is to be sent. An 8-cycle
(16 bit) transfer occurs when register data is to be sent in addition
to any status information.
Status transfer terminated. The PHY normally terminates a status
transfer by asserting idle on the CTL lines. If a bus reset is
pending, the PHY may also assert Grant on the CTL line
immediately following a complete status transfer.
DESCRIPTION
S[14:15]
(b)
SV01759
00
00
01
DATA RATE
S100
S200
S400
“data-on” indication
PDI1394P23
Preliminary data