isd-t360sb ETC-unknow, isd-t360sb Datasheet - Page 30

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isd-t360sb

Manufacturer Part Number
isd-t360sb
Description
Manufacturer
ETC-unknow
Datasheet
ISD-T360SB
1.
2.
1-22
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
CCLKSp
CCLKSh
CCLKSl
CDIh
CDIs
CFS0Ss
CFS0Sh
DIh
DIs
MWCKh
MWCKl
MWCKp
MWCLKh
MWCLKs
MWCSh
MWCSs
MWDIh
MWDIs
PWR
RSTw
Xh
Xl
Xp
Symbol
Guaranteed by design, but not fully tested.
Guaranteed by design, but not fully tested in power-down mode.
Figure
Codec Clock Period (slave)
Codec Clock High (slave)
Codec Clock Low (slave)
CDIN Hold
CDIN Setup
CFS0 Setup
CFS0 Hold
Data in Hold (D0:7)
Data in Setup (D0:7)
MICROWIRE Clock High (slave)
MICROWIRE Clock Low (slave)
MICROWIRE Clock Period
(slave)
MWCLK Hold
MWCLK Setup
MWCS Hold
MWCS Setup
MWDIN Hold
MWDIN Setup
Power Stable to RESET R.E.
RESET Pulse Width
CLKIN High
CLKIN Low
CLKIN Clock Period
1
Description
Table 1-10: Input Signals
2
At 2.0 V (both edges)
At 0.8 V (both edges)
After R.E. CTTL
Before R.E. CTTL
Before R.E. CCLK
After R.E. CTTL T1, T3 or TI
Before R.E. CTTL T1, T3 or TI
At 2.0 V (both edges)
At 0.8 V (both edges)
R.E. MWCLK to next R.E. MWCLK
After MWCS becomes inactive
Before MWCS becomes active
After F.E. MWCLK
Before R.E. MWCLK
After R.E. MWCLK
Before R.E. MWCLK
After V
At 0.8 V (both edges)
At 2.0 V (both edges)
At 0.8 V (both edges)
R.E. CLKIN to next R.E. CLKIN
R.E. CCLK to next R.E. CCLK
After R.E. CCLK
Reference Conditions
CC
reaches 4.5 V
Voice Solutions in Silicon
t
t
Min (ns)
30.0 ms
10.0 ms
X1p
X1p
100.0
100.0
2.5 µs
100.0
100.0
100.0
244.4
25.0
19.0
50.0
75.0
50.0
120
120
244
TBD
TBD
0.0
0.0
/2 – 5
/2 – 5
1—HARDWARE
Max (ns)

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